參數(shù)資料
型號(hào)： TAS3202PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 16/66頁
文件大?。?/td> 817K
代理商： TAS3202PAGR
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
6.3
I
2C Slave-Mode Operation
The I2C slave mode is the mode that is used to change configuration parameters during operation and to
perform program and coefficient downloads from a master device. The coefficient download operation in
slave mode can be used to replace the I2C master-mode EEPROM download. The TAS3202 supports
both random and sequential I2C transactions. The TAS3202 I2C slave address is 011010xy, where the first
six bits are the TAS3202 device address and bit x is CS0, which is set by the TAS3202 internal
microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00
address when no connection is made to the pin. Table 6-1 and Table 6-3 show all the legal addresses for
I2C slave and master modes.
The multiword transfers always store first word on the bus at a lower RAM address and increment such
that the last word in the transfer is stored with the highest target RAM address. Consecutive I2C frame
transfers increment target address such that the data in the last transfer is last in target memory address
space.
When the Memory Load Control Register (0×04) is written by the system controller, the TAS3202 updates
the status register by setting a error bit to indicate an error for the memory type that is being loaded. This
error bit is reset when the operation complete and a valid checksum has been received. For example,
when the micro program memory is being loaded, the TAS3202 sets a micro program memory error
indication in the status register at the start of the sequence. When the last byte of the micro program
memory and checksum is received, the TAS3202 clears the micro program memory error indication. This
enables the TAS3202 to preserve any error status indications that occur as a result of incomplete
transfers of data/ checksum error during a series of data and program memory load operations.
The checksum is always contained in the last two bytes of the data block. The I2C slave download is
terminated when a termination header with a zero-length byte-count file is received.
The status register always reflects status of EEPROM boot attempts, unless the user writes to the slave
control register. A write to the slave boot control register causes the EEPROM status register to reflect
slave boot attempt status.
Refer to Section 9.3 for formatting details.
NOTE
Once the micro program memory has been loaded, further updates to this memory are
prohibited until the device is reset. The TAS3202 I
2C block does respond to the broadcast
address (00h).
Copyright 2009–2011, Texas Instruments Incorporated
Microprocessor Controller
23
Product Folder Link(s): TAS3202
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