參數(shù)資料
型號(hào)： TAS3202PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 11/66頁
文件大小： 817K
代理商： TAS3202PAGR
Are
Clocks
Stable?
No
Yes
RESET Pin = Low
Enable Mute and
Wait for Completion
Change fMCLK
RESET Pin = High
After
TAS3202
Initializes,
Re-initialize
I C Registers
2
www.ti.com
SLES208B – JUNE 2009 – REVISED MARCH 2011
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure
When the serial audio port (SAP) is in the master mode, the SAP uses the XTAL_IN master clock to drive
the serial port clocks SCLK_OUT and LRCLK. When the SAP is in the slave mode, MCLK_IN, SCLK_IN,
and LRCLK_IN are input clocks. SCLK_OUT and LRCLK_OUT are derived from SCLK_IN and
LRCLK_IN, respectively.
See Clock Register (0x00), Section 9.1, for information on programming the clock register.
Table 5-1. TAS3202 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz)
FS
MCLK/
MCLK
SCLKIN
SCLK_IN
SCLK_OUT
PLL
SAMPLE
CH PER
LRCLK
CH PER
LRCLK
FDSPCLK
FREQ
RATE
FREQ
RATE
MULTIPLI
fDSPCLK/fS
RATE
SDIN
RATIO
SDOUT
(FS)
(MHz)
(× fS)
(MHz)
(× fS)
ER
(kHz)
(× fS)
Slave Mode, 2 Channels In, 2 Channels Out
44.1
2
512
22.579
64
2.822
64
2
64
5.5
124.2
2816
48
2
256
24.576
64
3.072
64
2
64
5.5
135.2
2816
Master Mode, 2 Channels In, 2 Channels Out
48
2
256
24.576
N/A
64
2
64
5.5
135.2
2816
Copyright 2009–2011, Texas Instruments Incorporated
Microprocessor Controller
19
Product Folder Link(s): TAS3202
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