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參數(shù)資料
| 型號： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 16/248頁 |
| 文件大小： | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
6
Lucent Technologies Inc.
List of Figures
Figure
Page
Figure 1. T7633 Block Diagram (One of Two Channels)........................................................................................ 15
Figure 2. T7633 Block Diagram: Receive Section (One of Two Channels)............................................................ 17
Figure 3. T7633 Block Diagram: Transmit Section (One of Two Channels)........................................................... 18
Figure 4. Pin Assignment ....................................................................................................................................... 19
Figure 5. Block Diagram of Line Interface Unit: Single Channel ............................................................................ 26
Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator.......................................................... 32
Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator...................................................................... 32
Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator....................................................... 33
Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................... 33
Figure 10. DSX-1 Isolated Pulse Template............................................................................................................ 37
Figure 11. ITU-T G.703 Pulse Template ................................................................................................................ 38
Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 42
Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator....................................................................................... 42
Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator........................................................... 43
Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 43
Figure 16. Line Termination Circuitry ..................................................................................................................... 48
Figure 17. T7633 Line Interface Unit Approximate Equivalent Analog I/O Circuits................................................ 49
Figure 18. Block Diagram of Framer Line Interface................................................................................................ 50
Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing...................... 51
Figure 20. T1 Frame Structure............................................................................................................................... 55
Figure 21. T1 Transparent Frame Structure........................................................................................................... 56
Figure 22. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections...................... 58
Figure 23. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe
Structures............................................................................................................................................... 66
Figure 24. CEPT Transparent Frame Structure ..................................................................................................... 68
Figure 25. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer................................... 73
Figure 26. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment
Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)...................................... 75
Figure 27. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode... 81
Figure 28. Transmit and Receive Sa Stack Accessing Protocol ............................................................................ 83
Figure 29. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode............................................. 87
Figure 30. Timing Specification for TFS, TLCK, and TPD in DS1 Mode................................................................ 87
Figure 31. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode.......................................... 88
Figure 32. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode............................ 88
Figure 33. Timing Specification for RCRCMFS in CEPT Mode.............................................................................. 89
Figure 34. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ............................................................. 89
Figure 35. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode................................................ 90
Figure 36. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode.......................................... 90
Figure 37. Relation Between RLCK1 and Interrupt (Pin 99)................................................................................... 91
Figure 38. Timing for Generation of LOPLLCK (Pin 39/143).................................................................................. 93
Figure 39. The T and V Reference Points for a Typical CEPT E1 Application....................................................... 96
Figure 40. Loopback and Test Transmission Modes............................................................................................ 101
Figure 41. 20-Stage Shift Register Used to Generate the Quasi-Random Signal................................................ 102
Figure 42. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ............................................... 103
Figure 43. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections.................... 108
Figure 44. Block Diagram for the Receive Facility Data Link Interface ................................................................ 109
Figure 45. Block Diagram for the Transmit Facility Data Link Interface ............................................................... 114
Figure 46. Local Loopback Mode......................................................................................................................... 120
Figure 47. Remote Loopback Mode..................................................................................................................... 121
Figure 48. T7633 Phase Detector Circuitry.......................................................................................................... 123
Figure 49. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))......... 129
Figure 50. CHIDTS Mode Concentration Highway Interface Timing.................................................................... 130
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