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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 127/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
117
Lucent Technologies Inc.
Facility Data Link (FDL)
(continued)
HDLC Operation
(continued)
CRC-16
For given user data bits, 16 additional bits that constitute an error-detecting code (CRC-16) are added by the
transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit
first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the
transmitted bits by using the ITU-T standard polynomial:
x
16
+ x
12
+ x
5
+ 1
The transmitter can be instructed to transmit a corrupted CRC by setting register FDL_PR2 bit 7 (FTBCRC) to 1.
As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flipping the least
significant bit of the transmitted CRC.
The receiver performs the same calculation on the received bits after destuffing and compares the results to the
received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch.
Transmit FDL FIFO
Transmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The
transmit FDL status register indicates how many additional bytes can be added to the transmit FIFO. The transmit
FDL interrupt trigger level register FDL_PR3 bit 0—bit 5 (FTIL) can be programmed to tailor service time intervals
to the system environment. The transmitter empty interrupt bit is set in the FDL interrupt status register FDL_SR0
bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register
FDL_PR3 bit 0—bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty
spaces exist. Overrunning the transmitter causes the last valid data byte written to be repeatedly overwritten,
resulting in missing data in the frame.
Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor.
However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a
transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the
transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the
tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not
written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the
transmitter has completed a frame, with a closing flag or an abort sequence, register FDL_SR0 bit 0 (FTDONE) is
set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1.
Sending 1-Byte Frames
Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data
bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is
written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte
frames are subject to underrun aborts. One-byte frames cannot be aborted with FTABT. Placing the transmitter in
1s-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not
empty, then 1-byte frames present no problems.
Transmitter Underrun
After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before
a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in
the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort
sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter
reports an underrun abort until the interrupt status register is read.
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