參數(shù)資料
型號(hào): T7633
廠商: Lineage Power
英文描述: Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器)
中文描述: 雙T1/E1的3.3伏短途終結(jié)者(雙T1/E1的3.3短通信距離終端器)
文件頁(yè)數(shù): 132/248頁(yè)
文件大?。?/td> 1459K
代理商: T7633
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
122
Lucent Technologies Inc.
Phase-Lock Loop Circuit
The T7633 allows for independent transmit path and receive path clocking. The device provides outputs to control
variable clock oscillators on both the transmit and receive paths. As such, the system may have both the transmit
and receive paths phase-locked to two autonomous clock sources.
The block diagram of the T7633 phase detector circuitry is shown in Figure 48 on page 123. The T7633 uses elas-
tic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of
2.048 Mbits/s to the line interface clock rate of either 1.544 Mbits/s or 2.048 Mbits/s.The transmit line side of the
T7633 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This
interface relies on the requirement that the PLLCK clock signal (variable) is phase-locked to the RCHICK clock sig-
nal (reference). When this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer
that would result in corrupting data and no indication will be given. Typically, a variable clock oscillator (VCXO) is
used to drive the PLLCK signal. The T7633 provides a phase error signal (PLLCK-EPLL) that can be used to con-
trol the VCXO. The PLLCK-EPLL signal is generated by monitoring the divided-down PLLCK (DIV-PLLCK) and
RCHICK (DIV-RCHICK) signals. The DIV-RCHICK signal is used as the reference to determine the phase differ-
ence between DIV-RCHICK and DIV-PLLCK. While DIV-RCHICK and DIVPLLCK are phase-locked, the PLLCK-
EPLL signal is in a high-impedance state. A phase difference between DIV-RCHICK and DIV-PLLCK drives
PLLCK-EPLL to either 5 V or 0 V. An RC circuit (typically, R = 1 k
and C = 0.1
μ
F) is used to filter these PLLCK-
EPLL pulses to control the VCXO.
The system can force TCHICK to be phase-locked to RLCK by using RLCK as a reference signal to control a VCXO
that is sourcing the TCHICK signal. The T7633 uses the receive line signal (RLCK) as the reference and the TCH-
ICK signal as the variable signal. The T7633 provides a phase error signal (TCHICK-EPLL) that can be used to
control the VCXO generating TCHICK. The TCHICK-EPLL signal is generated by monitoring the divided-down
TCHICK signal (DIV-TCHICK) and RLCK (DIV-RLCK) signals. The DIV-RLCK signal is used as the reference to
determine the phase difference between DIV-TCHICK and DIV-RLCK. While DIV-RLCK and DIV-TCHICK are
phase-locked, the TCHICK-EPLL signal is in a high-impedance state. A phase difference between DIV-RLCK and
DIV-TCHICK drives TCHICK-EPLL to either 5 V or 0 V. An RC circuit (typically, R = 1 k
and C = 0.1
μ
F) is used to
filter these TCHICK-EPLL pulses to control the VCXO. In this mode, the T7633 can be programmed to act as a
master timing source and is capable of generating the system frame synchronization signal through the TCHIFS
pin by setting FRM_PR45 bit 4 to 1.
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