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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 135/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
125
Lucent Technologies Inc.
Concentration Highway Interface (CHI)
Each framer has a dual, high-speed, serial interface to the system known as the concentration highway interface
(CHI). This flexible bus architecture allows the user to directly interface to other Lucent components which use this
interface, as well as to Mitel
1
and AMD
2
TDM highway interfaces, with no glue logic. Configured via the highway
control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configura-
tions.
The following is a list of the CHI features:
1. Lucent Technologies standard interface for communication devices.
2. Two pairs of transmit and receive paths to carry data in 8-bit time slots.
3. Programmable definition of highways through offset and clock-edge options which are independent for transmit
and receive directions.
4. Programmable idle code substitution of received time slots.
5. Programmable 3-state control of each transmit time slot.
6. Independent transmit and receive framing signals to synchronize each direction of data flow.
7. An 8 kHz frame synchronization signal internally generated from the received line clock.
8. Compatible with Mitel and AMD PCM highways.
Supported is the optional configuration of the CHI which presents the signaling information along with the data in
any framing modes when the device is programmed for the associated signaling mode (ASM). This mode is dis-
cussed in the signaling section.
Data can be transmitted or received on either one of two interface ports, called CHIDATA and CHIDATAB. The user-
supplied clocks (RCHICLK and TCHICLK) control the timing on the transmit or receive paths. Individual time slots
are referenced to the frame synchronization (RCHIFS and TCHIFS) pulses. Each frame consists of 32 time slots at
a programmable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s requiring a clock (TCHICK and
RCHICK) of the same rate. Alternatively, a mode is supported in which the clocks (TCHICK and RCHICK) can be
twice the data rate, the CMS mode. This mode is controlled by register FRM_PR45 bit 1. The clock and data rates
of the transmit and receive highways are programmed independently.
Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s,
4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is achieved by means of stuffing eight idle time slots into the existing
twenty-four time slots of the T1 frame. Idle time slots can occur every fourth time slot (starting in the first, second,
third, or fourth time slot) or be grouped together at the end of the CHI frame as described in register FRM_PR43
bit 0—bit 2. The positioning of the idle time slots is the same for transmit and receive directions. Idle time slots con-
tain the programmable code of register FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA
interface to a high-impedance state for the interval of the disabled time slots.
1.Mitel is a registered trademark of Mitel Corporation.
2.AMD is a registered trademark of Advanced Micro Devices, Inc.
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