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參數資料
| 型號： | T35L6432A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數： | 6/15頁 |
| 文件大小： | 1347K |
| 代理商： | T35L6432A |
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 6
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
TRUTH TABLE
OPERATION
ADDRESS
CE CE2 CE2 ZZADSP ADSC ADV WRITE OE CLK DQ
USED
None
H
X
X
L
X
None
L
X
L
L
L
None
L
H
X
L
L
None
L
X
L
L
H
None
L
H
X
L
H
None
X
X
X
H
X
External
L
L
H
L
L
External
L
L
H
L
L
External
L
L
H
L
H
External
L
L
H
L
H
External
L
L
H
L
H
Next
X
X
X
L
H
Next
X
X
X
L
H
Next
H
X
X
L
X
Next
H
X
X
L
X
Next
X
X
X
L
H
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Snooze Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue
Burst
WRITE Cycle, Continue
Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
X
High-Z
L-H
L-H High-Z
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
L-H
Q
D
Q
Q
Q
D
Next
H
X
X
L
X
H
L
L
X
L-H
D
Current
Current
Current
Current
Current
Current
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
X
X
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
Q
Q
D
D
Note:
1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or
more byte write enable signals
(
BW1
,
BW2
,
BW3
or
BW4
)
and
BWE
are LOW, or
GW
equals LOW. WRITE= H means all byte write signal are HIGH.
2.
BW1
= enables write to DQ1-DQ8.
BW2
= enables write to DQ9-DQ16.
BW3
= enables write to
DQ17-DQ24.
BW4
=enables write to DQ25-DQ32.
3. All inputs except
OE
must meet setup and hold times around the rising edge ( LOW to HIGH)
of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
OE
must be HIGH before the input data
required setup time plus High-Z time for
OE
and staying HIGH throughout the input data hold
time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
ADSP
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge
of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
相關PDF資料 |
PDF描述 |
|---|---|
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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