TE
CH
tm
SYNCHRONOUS
BURST SRAM
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision: A
64K x 32 SRAM
3.3V supply, fully registered inputs and
outputs, burst counter
FEATURES
E
Fast Access times: 4.5, 5, 6, 7, and 8ns
E
Fast clock speed: 125,100, 83, 66, and 50 MHz
E
Provide high performance 3-1-1-1 access rate
E
Fast
OE
access times: 4.5, 5 and 6ns
E
Single 3.3V +10%/-5% power supply
E
Common data inputs and data outputs
E
BYTE WRITE ENABLE and GLOBAL WRITE
control
E
Three chip enables for depth expansion and
address pipelining
E
Address, control, input, and output pipelined
registers
E
Internally self-timed WRITE CYCLE
E
WRITE pass-through capability
E
Burst control pins ( interleaved or linear burst
sequence)
E
High density, high speed packages
E
Low capacitive bus loading
E
High 30pF output drive capability at rated access
time
E
SNOOZE MODE for reduced power standby
E
Single cycle disable ( Pentium
TM
BSRAM
compatible )
OPTIONS
TIMING
4.5ns access/8ns cycle
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
100-pin QFP
100-pin TQFP
MARKING
-4.5
-5
-6
-7
-8
Q
T
Part Number Examples
PART NO.
T35L6432A-5Q
Pkg.
Q
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
T35L6432A-5T
T
PIN ASSIGNMENT
(Top View)
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC
NC
DQ1
DQ2
VCCQ
VSSQ
DQ3
DQ4
DQ5
DQ6
VSSQ
VCCQ
DQ7
DQ8
ZZ
VCC
NC
VSS
DQ9
DQ10
VCCQ
VSSQ
DQ11
DQ12
DQ13
DQ14
VSSQ
VCCQ
DQ15
DQ16
NC
1
2
11
12
10
9
8
7
6
5
4
3
18
19
17
16
15
14
13
28
29
27
26
25
24
23
22
21
20
30
31
41
40
39
38
37
36
35
34
33
32
49
48
47
46
45
44
43
42
50
60
59
58
57
56
55
54
53
52
51
70
69
68
67
66
65
64
63
62
61
80
79
78
77
76
75
74
73
72
71
95
96
88 87 86 85 84 83 82 81
90
91
92
93
94
89
100 99 98 97
A
A
B
G
C
V
V
C
B
B
B
B
C
C
A
A
A
O
A
A
N
V
N
N
A
A
N
V
A
A
A
A
A
N
A
A
A
M
A
A
100-pin QFP
or
100-pin TQFP
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS
design
using
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6432A SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining
advanced
triple-layer