TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
INTERLEAVED BURST ADDRESS TABLE
(MODE = NC/VCC)
First Address
(external)
A...A00
A...A01
A...A10
A...A11
Second Address
(internal)
A...A01
A...A00
A...A11
A...A10
Third Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth Address
(internal)
A...A11
A...A10
A...A01
A...A00
LINEAR BURST ADDRESS TABLE
(MODE = GND)
First Address
(external)
A...A00
A...A01
A...A10
A...A11
Second Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth Address
(internal)
A...A11
A...A00
A...A01
A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
READ
READ
WRITE one byte
WRITE all byte
WRITE all byte
GW
H
H
H
H
L
BWE
H
L
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3
X
H
H
L
X
BW4
X
H
H
L
X
WRITE PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
OPERATION
Initiate WRITE cycle, all bytes All L2,3Initiate READ cycle
Address= A(n-1), data= D(n-1)
Initiate WRITE cycle, all bytes All L2,3No new cycle
Address= A(n-1), data= D(n-1)
Initiate WRITE cycle, all bytes All L2,3No new cycle
Address= A(n-1), data= D(n-1)
Initiate WRITE cycle, one bytes ONE L2No new cycle
Address= A(n-1), data= D(n-1)
PRESENT CYCLE
OPERATION
NEXT CYCLE
OPERATION
Read D(n)
BWn
CE
BWn
OE
L
H
L
Register A(n), Q= D(n-1)
H
H
L
No carry-over from
previous cycle
H No carry-over from
previous cycle
L
No carry-over from
previous cycle
Q = D(n-1)
H
H
Q = HIGH-Z
H
H
Q = D(n-1) for one byte
Note:
1. Previous cycle may be any cycle(non-burst, burst, or wait).
2.
BWE
is LOW for individual byte WRITE.
3.
GW
= LOW yields the same result for all-byte WRITE operation.