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參數(shù)資料
| 型號(hào)： | T35L6432A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 1347K |
| 代理商： | T35L6432A |
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TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision: A
GENERAL DESCRIPTION
(continued)
chip enable (
CE
), depth- expansion chip enables
(
CE2
and
CE2),burst
(
ADSC
,
ADSP
, and
ADV
), write enables
(
BW1
,
BW2
,
BW3
,
BW4
, and
BWE
), and
global write (
GW
).
Asynchronous inputs include the output
enable (
OE
),Snooze enable (ZZ) and burst mode
control (MODE). The data outputs (Q), enabled
by
OE
, are also asynchronous.
Addresses and chip enables are registered
with either address status processor (
ADSP
) or
address status controller (
ADSC
) input pins.
Subsequent burst addresses can be internally
generated as controlled by the burst advance pin
(
ADV
).
Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to four bytes
control
inputs
wide as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-DQ16.
BW3
controls DQ17-DQ
24.
BW4
controls DQ25-DQ32.
BW1
,
BW2
,
BW3
, and
BW4
can be active only with
BWE
being LOW.
GW
being LOW causes all
bytes to be written. WRITE pass-through
capability allows written data available at the
output for the immediately next READ cycle.
This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing
system performance. The T35L6432A operates
from a 3.3V +10%/-5% power supply. The device
is ideally suited for Pentium
, 680X0, and Power
PC
systems and for systems that are benefited
from a wide synchronous data bus.
FUNCTIONAL BLOCK DIAGRAM
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
BYTE 1
WRITE REGISTER
BYTE 3
WRITE REGISTER
WRITBYTE 2
ADDRESS
REGISTER
DO D1 Q1
BINARY
& LOGIC
CLR
Q0
BYTE 1
WRITE DRIVER
WRIBYTE 2
BYTE 3
WRITE DRIVER
BYTE 4
WRITE DRIVER
16
16
14
16
A0
A1
A1'
A0'
64K x 8 x 4
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
INPUT
REGISTERS
8
8
8
8
8
8
8
8
32
32
32
DQ1
E
E
E
DQ32
4
A0-A15
MODE
ADV
CLK
ADSC
ADSP
BW4
BW3
BW2
BW1
CE
CE2
CE2
OE
GW
BWE
PIPELINED
ENABLE
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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