參數(shù)資料
型號: STPCE1HEBI
廠商: 意法半導(dǎo)體
英文描述: X86 Core General Purpose PC Compatible System - on - Chip
中文描述: x86內(nèi)核兼容的通用計算機系統(tǒng)-關(guān)于-芯片
文件頁數(shù): 71/87頁
文件大?。?/td> 1356K
代理商: STPCE1HEBI
DESIGN GUIDELINES
Release 1.3 - January 29, 2002
71/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.4. PLACE AND ROUTE
RECOMMENDATIONS
6.4.1. GENERAL RECOMMENDATIONS
Some STPC Interfaces run at high speed and
need to be carefully routed or even shielded like:
1) Memory Interface
2) PCI bus
3) 14 MHz oscillator stage
All clock signals have to be routed first and
shielded for speeds of 27MHz or higher. The high
speed signals follow the same constraints, as for
the memory and PCI control signals.
The next interfaces to be routed are Memory and
PCI.
All the analog noise-sensitive signals have to be
routed in a separate area and hence can be
routed indepedently.
Figure 6-15. Shielding signals
ground ring
ground pad
shielded signal line
ground pad
shielded signal lines
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