參數(shù)資料
型號: STPCE1HEBI
廠商: 意法半導體
英文描述: X86 Core General Purpose PC Compatible System - on - Chip
中文描述: x86內(nèi)核兼容的通用計算機系統(tǒng)-關于-芯片
文件頁數(shù): 39/87頁
文件大?。?/td> 1356K
代理商: STPCE1HEBI
ELECTRICAL SPECIFICATIONS
Release 1.3 - January 29, 2002
39/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
4.5.2 RESET SEQUENCE
Figure 4-4
describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Strap Options
SYSRSTI#
SYSRSTO#
14 MHz
VALID CONFIGURATION
HCLK
PCI_CLK
2.3 ms
ISACLK
1.6 V
MD[63:0]
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