參數資料
型號： STPCE1HEBI
廠商： 意法半導體
英文描述： X86 Core General Purpose PC Compatible System - on - Chip
中文描述： x86內核兼容的通用計算機系統(tǒng)-關于-芯片
文件頁數： 69/87頁
文件大小： 1356K
代理商： STPCE1HEBI
DESIGN GUIDELINES
Release 1.3 - January 29, 2002
69/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING
Some of the ISA bus signals are dynamically
multiplexed to optimize the pin count.
Figure 6-12
describes how to implement the external glue
logic to demultiplex the IDE and ISA interfaces. In
Local Bus mode the two buffers are not needed
and the NAND gates can be simplified to inverters.
6.3.8. BASIC AUDIO USING IDE INTERFACE
When the application requires only basic audio
capabilities, an audio DAC on the IDE interface
can avoid using a PCI-based audio device. This
low cost solution is not CPU consuming thanks to
the DMA controller implemented in the IDE
controller and can generate 16-bit stereo sound.
The clock speed is programmable when using the
speaker output.
Figure 6-13. Basic audio on IDE
Figure 6-12. Typical IDE / ISA Demultiplexing
MASTER#
74xx245
DIR
RMRTCCS#
KBCS#
RTCRW#
RTCDS
SA[19:8]
A
B
OE
ISAOE#
STPC bus / DD[15:0]
LA[24]
LA[25]
LA[22]
LA[23]
SCS1#
SCS3#
PCS1#
PCS3#
74xx74
16
Q
Q
DD[15:0]
PCS1
PDIOW#
D
PR
RST
D[15:0]
CS#
WR#
A/B
Audio Out
Right
Left
Stereo DAC
PDRQ
SYSRSTO#
Speaker
Vcc
Vcc
Vcc
STPC
Q
Q
D
PR
RST
Note * : the inverter can be removed when the DAC CS# is directly connected to GND
*
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