參數(shù)資料
型號(hào): STPCE1HEBI
廠商: 意法半導(dǎo)體
英文描述: X86 Core General Purpose PC Compatible System - on - Chip
中文描述: x86內(nèi)核兼容的通用計(jì)算機(jī)系統(tǒng)-關(guān)于-芯片
文件頁(yè)數(shù): 68/87頁(yè)
文件大小: 1356K
代理商: STPCE1HEBI
DESIGN GUIDELINES
68/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
The
implementation of the external glue logic for DMA
Request time-multiplexing and DMA Acknowledge
demultiplexing. Like for the interrupt lines, this
Figure 6-11. Typical DMA multiplexing and demultiplexing
figure
below
describes
a
complete
logic can be simplified when only few DMA
channels are used in the application.
This glue logic is not needed in Local bus mode as
it does not support DMA transfers.
74x153
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1Y
1G
DRQ[0]
DRQ[1]
DRQ[2]
DRQ[3]
DRQ[4]
DRQ[5]
DRQ[6]
DRQ[7]
DREQ_MUX[0]
2G
2Y
DREQ_MUX[1]
74x138
Y0#
Y1#
Y2#
Y3#
Y4#
Y5#
Y6#
Y7#
A
B
G2B
DACK0#
DACK1#
DACK2#
DACK3#
C
G2A
ISA_CLK2X
ISA_CLK
ISA, Refresh
ISA, PIO
ISA, FDC
ISA, PIO
Slave DMAC
ISA
ISA
ISA
G1
DMA_ENC[0]
DMA_ENC[1]
DMA_ENC[2]
DACK5#
DACK6#
DACK7#
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