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參數(shù)資料
| 型號： | STPCC0310BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 42/51頁 |
| 文件大?。?/td> | 836K |
| 代理商： | STPCC0310BTC3 |
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BOARD LAYOUT
47/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.3.7 Data Read (MD[63:0])
The data read simulation circuit is shown below..
6.3.8 Data Mask (DQM[7:0])
The data mask load is quite similar to that of the
data signals.
6.3.9 Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing unless the mem-
ory controller can be designed to set up these sig-
nals one cycle in advance. The simulations show
that for these signals the best way to drive them is
to use a parallel termination. For applications
where speed is not so critical series termination
can be used as this will save power. Using a low
impedance such as 50W for these critical traces is
recommended as it both reduces the delay and
the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals for
unbuffered DIMMs. When using registered DIMMs
the other signals will probably be just as critical as
the address/control signals so to gain maximum
benefit from using registered DIMMs the timings
should also be considered in that situation. Using
lower impedance traces is also beneficial for the
other signals but if their timing is not as critical as
the address/control signals they could use the de-
fault value. Using a lower impedance implies us-
ing wider traces which may have an impact on the
routing of the board.
Figure 6-17. Data read equivalent circuit
125mm
(0.9ns)
DIMM2
DIMM3
DIMM4
10mm
10W
SDRAM
DQ
DIMM1
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