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參數(shù)資料
| 型號： | STPCC0310BTC3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA388 |
| 封裝： | PLASTIC, BGA-388 |
| 文件頁數(shù)： | 41/51頁 |
| 文件大?。?/td> | 836K |
| 代理商： | STPCC0310BTC3 |
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BOARD LAYOUT
46/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.3.4 Address & Control Signals
This group encompasses the memory address
MA[12:0], bank address BA[0,1], RAS, CAS and
write enable WE signals. The load of the DIMM
module on these signals is the most important
oneand depends upon the type of SDRAM com-
ponents used (x4, x8 or x16) and whether the
DIMM module is single or dual row. The capacitive
loading of the SDRAM inputs alone for an x8 sin-
gle row DIMM will be about 30-40pF. An equiva-
lent circuit for the timing simulation is shown in
Figure 6-14 Most of the delays are due to the PCB
traces and loading rather than the pad itself.
6.3.5 Chip Select Signals (CS#[3:0])
There are 4 chip select pins per DIMM. Chip se-
lects 0 and 2 are always used to select the first
row of SDRAMs and chip selects 1 and 3 select
the second row on dual bank SDRAMs. The chip
select outputs only have to drive one DIMM each
6.3.6 Data Write (MD[63:0])
The load on the data signals is much lower than
the address/control signals for an unbuffered
DIMM. For a registered DIMM the data signals are
the only memory pins of the DIMM which are not
registered. For the design to get maximum benefit
from using registered DIMMs the timings should
be compared to the timings for registered DIMMs
for the other pins..
Figure 6-14. Address/control equivalent circuit
DIMM4
DIMM3
DIMM2
DIMM1
Rterm
100mm
(0.7ns)
10mm
Zpcb
Figure 6-15. CS# equivalent circuit
130mm
(0.9ns)
DIMM
CS[0]
CS[2]
Figure 6-16. Data write equivalent circuit
DIMM4
DIMM3
DIMM2
DIMM1
125mm
(0.9ns)
10mm
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