參數(shù)資料
型號(hào)： STP1081ABGA-150
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 28/32頁(yè)
文件大小： 478K
代理商： STP1081ABGA-150
5
Companion Device for 250/300 MHz UltraSPARC-II Systems
UltraSPARC
-II Data Buffer (UDB-II)
STP1081
Preliminary
July 1997
Error Correction Code (ECC) and Parity
The UDB-II supports error detection and correction on the system side using an ECC of 8 bits per 64 data bits.
It corrects single errors and detects double errors and nibble errors. As implemented in UDB-II, the code has
separate trees for ECC checking and correcting. Correctable errors are xed in the same cycle during which
they are detected. The UDB-II will log the syndrome for each corrected error (to help in diagnosing multi-bit
errors).
There are some CSR read/write registers for enabling or disabling ECC. These registers are accessible through
special ASI load or store activity.
There are two trap modes for UltraSPARC-II due to errors:
Trap on any ECC error
Trap on non-correctable ECC error
No automatic updating of memory occurs when a single-bit ECC error is corrected. Software may update
memory with corrected data, maintaining multiprocessor cache coherency, by using cache ushes and
compare-and-swap.
Data is protected on the UltraSPARC-II side using parity (odd parity), and on the UPA side using ECC. Parity
is generated for data going from the UDB-II to the UltraSPARC-II, while syndrome bits are generated for data
going from the UDB-II to the UPA. Data coming to the UDB-II from the UltraSPARC
TM-II is checked for parity
errors, while data coming from the UPA to the UDB-II is checked for ECC.
ECC Code Used
ECC is performed on a 64-bit boundary, using Kaneda SEC/DED/S4ED codes. There are eight check bits per
64-bit boundary. The code provides detection of single- and double-bit errors, as well as three- and four-bit
errors within a nibble. In addition, the code provides correction of any single bit error on 64-bit data.
ECC Control and Status Registers
Memory is not updated after an error is corrected. Parity errors are detected by the XOR of the eight
P_syndrome bits. During ECC checking, the syndrome for the rst correctable error is logged, and is only
overwritten by the syndrome for an uncorrectable error. When there is an uncorrectable error, bad parity is
forced on to data going out to the UltraSPARC-II. In diagnostic mode, a check bit vector of ECC bits is forced
for data going from UDB-II to UPA.
Reserved
Figure 4. ECC and Parity Fault Status Register (Duplicated in UDB_H and UDB_L)
CE
UE
E_SYNDROME[7:0]
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