
SEC ASIC
4-65
STD110
PSCKDCby
LVCMOS Level Input Clock Drivers
Switching Characteristics
(Typical process, 25
°
C, 2.5V, t
R
/t
F
= 3.00ns, SL: Standard Load)
PSCKDCU2
PSCKDCU4
PSCKDCU6
PSCKDCU8
Path
Parameter
Delay [ns]
SL = 2
0.181
0.140
0.810
0.879
<
Delay Equations [ns]
Group1*
0.174 + 0.003*SL
0.133 + 0.004*SL
0.807 + 0.001*SL
0.875 + 0.002*SL
Group2*
0.128 + 0.003*SL
0.100 + 0.004*SL
0.804 + 0.001*SL
0.873 + 0.002*SL
Group3*
0.102 + 0.003*SL
0.086 + 0.004*SL
0.802 + 0.001*SL
0.873 + 0.002*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 482, *Group2 : 482 <
Path
Parameter
Delay [ns]
SL = 2
0.243
0.179
1.055
1.117
<
Delay Equations [ns]
Group1*
0.240 + 0.002*SL
0.175 + 0.002*SL
1.053 + 0.001*SL
1.115 + 0.001*SL
Group2*
0.181 + 0.002*SL
0.124 + 0.002*SL
1.054 + 0.001*SL
1.112 + 0.001*SL
Group3*
0.141 + 0.002*SL
0.098 + 0.002*SL
1.052 + 0.001*SL
1.108 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 962, *Group2 : 962 <
Path
Parameter
Delay [ns]
SL = 2
0.301
0.221
1.255
1.315
<
Delay Equations [ns]
Group1*
0.299 + 0.001*SL
0.219 + 0.001*SL
1.254 + 0.000*SL
1.314 + 0.001*SL
Group2*
0.233 + 0.001*SL
0.158 + 0.001*SL
1.264 + 0.000*SL
1.311 + 0.001*SL
Group3*
0.187 + 0.001*SL
0.121 + 0.001*SL
1.261 + 0.000*SL
1.306 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1443, *Group2 : 144 <
Path
Parameter
Delay [ns]
SL = 2
0.352
0.260
1.428
1.487
<
Delay Equations [ns]
Group1*
0.350 + 0.001*SL
0.258 + 0.001*SL
1.427 + 0.000*SL
1.486 + 0.000*SL
Group2*
0.282 + 0.001*SL
0.194 + 0.001*SL
1.446 + 0.000*SL
1.484 + 0.000*SL
Group3*
0.231 + 0.001*SL
0.148 + 0.001*SL
1.444 + 0.000*SL
1.479 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1923, *Group2 : 1923 <