
SEC ASIC
3-376
MDL110
FDS2S/FDS2SD2
D Flip-Flop with Synchronous Clear, Scan, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C, 2.5V, Unit = ns)
Value (ns)
FDS2S
0.498
0.000
0.522
0.000
0.440
0.311
0.627
0.000
0.506
0.016
Input Load (SL)
Gate Count
FDS2S
FDS2S
CK
0.6
FDS2SD2
CK
0.6
FDS2SD2
D
0.5
CRN
0.6
TI
0.5
TE
1.2
D
0.5
CRN
0.6
TI
0.6
TE
1.2
8.00
8.67
Parameter
Symbol
FDS2SD2
0.500
0.000
0.521
0.000
0.431
0.329
0.609
0.000
0.382
0.033
Input Setup Time (D to CK)
Input Hold Time (D to CK)
Input Setup Time (CRN to CK)
Input Hold Time (CRN to CK)
Pulse Width Low (CK)
Pulse Width High (CK)
Input Setup Time (TI to CK)
Input Hold Time (TI to CK)
Input Setup Time (TE to CK)
Input Hold Time (TE to CK)
t
SU
t
HD
t
SU
t
HD
t
PWL
t
PWH
t
SU
t
HD
t
SU
t
HD
Q
QN
D
TE
CK
CRN
TI
QN
Q
CL
CLB
CL
CLB
CLB
CL
CRN
TEB
CL
CK
CLB
D
TI
TE
TE
TE
TEB
CL
CLB
Truth Table
D
CRN
TI
TE
CK
Q
(n+1)
0
1
0
0
1
Q (n) QN (n)
QN
(n+1)
1
0
1
1
0
0
1
x
x
x
x
1
1
0
x
x
x
x
x
x
0
1
x
0
0
0
1
1
x