
SEC ASIC
3-368
MDL110
FD8S/FD8SD2
D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Input Load (SL)
Gate Count
FD8S
FD8S
RN
1.5
FD8SD2
RN
1.5
FD8SD2
D
0.4
CKN
0.6
SN
1.6
TI
0.6
TE
1.2
D
0.4
CKN
0.6
SN
1.6
TI
0.6
TE
1.2
8.67
9.00
Q
QN
D
TI
TE
CKN RN
SN
CLBN
CLN
CLN
CLBN
CLN
CLBN
CLBN
CLN
CKN
CLN
CLBN
TE
TEB
TE
SN
RN
RN
SN
Q
QN
D
TE
TI
TEB
SN
SN
RN
RN
Truth Table
D
TI
TE
CKN
RN
SN
Q
(n+1)
0
1
0
1
1
0
0
Q (n) QN (n)
QN
(n+1)
1
0
1
0
0
1
0
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
0
0
1
1
x
x
x
x
1
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
x
x
x