
MDL110
3-319
SEC ASIC
FD2S/FD2SD2
D Flip-Flop with Reset, Scan, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements
(Typical process, 25
°
C, 2.5V, Unit = ns)
Value (ns)
FD2S
0.405
0.133
0.491
0.137
0.528
0.137
0.480
0.348
0.258
0.000
0.769
Input Load (SL)
Gate Count
FD2S
FD2S
RN
1.4
FD2SD2
RN
1.4
FD2SD2
D
0.5
CK
0.6
TI
0.5
TE
1.2
D
0.5
CK
0.6
TI
0.5
TE
1.2
7.67
8.00
Parameter
Symbol
FD2SD2
0.409
0.126
0.495
0.130
0.525
0.128
0.483
0.372
0.294
0.000
0.772
Input Setup Time (D to CK)
Input Hold Time (D to CK)
Input Setup Time (TI to CK)
Input Hold Time (TI to CK)
Input Setup Time (TE to CK)
Input Hold Time (TE to CK)
Pulse Width Low (CK)
Pulse Width High (CK)
Pulse Width Low (RN)
Recovery Time (RN to CK)
Removal Time (RN to CK)
t
SU
t
HD
t
SU
t
HD
t
SU
t
HD
t
PWL
t
PWH
t
PWL
t
RC
t
RM
Q
QN
D
TI
TE
CK RN
CL
CLB
Q
CLB
CL
QN
CK
CL
CLB
TE
TEB
TE
RN
RN
RN
D
TE
TI
TEB
CLB
CLRN
CL
CLB
Truth Table
D
TI
TE
CK
RN
Q
(n+1)
0
1
0
1
0
Q(n)
QN
(n+1)
1
0
1
0
1
QN(n)
0
1
x
x
x
x
x
x
0
1
x
x
0
0
1
1
x
x
1
1
1
1
0
1
x