
SEC ASIC
3-297
STD110
OAK_DUCLK10/OAK_DUCLK16
2 Phase Clock Generator Buffer (1ns/1.6ns Non-overlapped)
Switching Characteristics
OAK_DUCLK10
(Typical process, 25
°
C, 2.5V, t
R
/t
F
= 0.21ns, SL: Standard Load)
OAK_DUCLK16
Path
Parameter
Delay [ns]
SL = 2
0.079
0.081
2.319
1.349
0.079
0.081
2.391
1.263
<
Delay Equations [ns]
Group1*
0.073 + 0.003*SL
0.073 + 0.004*SL
2.313 + 0.003*SL
1.342 + 0.003*SL
0.071 + 0.004*SL
0.073 + 0.004*SL
2.385 + 0.003*SL
1.256 + 0.003*SL
Group2*
0.070 + 0.004*SL
0.074 + 0.004*SL
2.317 + 0.002*SL
1.347 + 0.002*SL
0.071 + 0.004*SL
0.073 + 0.004*SL
2.389 + 0.002*SL
1.260 + 0.002*SL
Group3*
0.047 + 0.004*SL
0.054 + 0.004*SL
2.331 + 0.002*SL
1.365 + 0.002*SL
0.048 + 0.004*SL
0.054 + 0.004*SL
2.402 + 0.002*SL
1.278 + 0.002*SL
A to CK
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
A to CKB
*Group1 : SL < 4, *Group2 : =
Path
Parameter
Delay [ns]
SL = 2
0.088
0.094
3.338
1.875
0.088
0.093
3.409
1.788
<
Delay Equations [ns]
Group1*
0.082 + 0.003*SL
0.088 + 0.003*SL
3.332 + 0.003*SL
1.868 + 0.004*SL
0.082 + 0.003*SL
0.086 + 0.003*SL
3.403 + 0.003*SL
1.781 + 0.004*SL
Group2*
0.080 + 0.004*SL
0.085 + 0.004*SL
3.337 + 0.002*SL
1.873 + 0.002*SL
0.078 + 0.004*SL
0.085 + 0.004*SL
3.408 + 0.002*SL
1.786 + 0.002*SL
Group3*
0.053 + 0.004*SL
0.064 + 0.004*SL
3.352 + 0.002*SL
1.894 + 0.002*SL
0.053 + 0.004*SL
0.064 + 0.004*SL
3.423 + 0.002*SL
1.807 + 0.002*SL
A to CK
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
A to CKB
*Group1 : SL < 4, *Group2 : =