參數(shù)資料
型號(hào)： ST72E85A5G0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4.332 MHz, MICROCONTROLLER, CQFP80
封裝： WINDOWED, CERAMIC, QFP- 80
文件頁數(shù)： 44/117頁
文件大?。?/td> 748K
代理商： ST72E85A5G0
32/117
ST7285C
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
This TR factor is used only when the PSBRT fine
tuning factor is equal to 0; otherwise, TR is re-
placed by the PSBRT dividing factor.
Bit-2 = SCR2
Receiver rate divisor MSB
Bit-1 = SCR1
Receiver rate divisor NSB
Bit-0 = SCR0
Receiver rate divisor LSB
These 3 bits, in conjunction with the 2 previous bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode..
This RR factor is used only when the PSBRR fine
tuning factor is equal to 0; otherwise, RR is re-
placed by the PSBRR dividing factor.
4.2.7.6 External Receive Prescaler Division
Register (PSCBRR)
Address: 0055h
—
Read/Write
Reset Value: 00h
Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit.
When the register is set to 00h, the conventional
Baud Rate Generator is used for the receive cir-
cuit, otherwise the master clock frequency is divid-
ed by the binary factor set in the PSCBRR register
(in the range 1 to 255).
4.2.7.7 External Transmit Prescaler Division
Register (PSCBRT)
Address: 0057h
—
Read/Write
Reset Value: 00h
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
When the register is set to 00h, the conventional
Baud Rate Generator is used for the transmit cir-
cuit, otherwise the master clock frequency is divid-
ed by the binary factor set in the PSCBRTregister
(in the range 1 to 255).
SCT2
SCT1
SCT0
TR dividing factor
00
0
1
00
1
2
01
0
4
01
1
8
10
0
16
10
1
32
11
0
64
1
128
SCR2
SCR1
SCR0
RR dividing factor
00
0
1
00
1
2
01
0
4
01
1
8
10
0
16
10
1
32
11
0
64
1
128
76
5
4321
0
PRBR
7
PRBR
6
PRBR
5
PRBR
4
PRBR
3
PRBR
2
PRBR
1
PRBR
0
76
5
4321
0
PTBR
7
PTB R
6
PTBR
5
PTB R
4
PTBR
3
PTB R
2
PTBR
1
PTB R
0
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