參數(shù)資料
型號(hào)： ST72361AR9TC
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 80/224頁(yè)
文件大小： 4821K
代理商： ST72361AR9TC
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ST72361-Auto
170/224
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.9.3.2 A/D Conversion
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
ADC Conversion mode
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
10.9.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
10.9.3.4 ADCDR consistency
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
To guarantee consistency:
– The ADCDRL and the ADCDRH registers are
locked when the ADCCRL is read
– The ADCDRL and the ADCDRH registers are
unlocked when the ADCDRH register is read
or when ADON is reset.
This is important, as the ADCDR register will not
be updated until the ADCDRH register is read.
10.9.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
10.9.5 Interrupts
None.
Mode
Description
WAIT
No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time tSTAB (see
Electrical Characteristics) before accurate
conversions can be performed.
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