- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25648 > ST72361AR9TC (STMICROELECTRONICS) 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | ST72361AR9TC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 54/224頁 |
| 文件大?。?/td> | 4821K |
| 代理商： | ST72361AR9TC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁
ST72361-Auto
147/224
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:2 Same function as in SCI mode, please re-
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details please refer to
– In LIN slave mode, when RDRF is set, the soft-
ware can not set or clear the RWU bit.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF = 1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
1: LDIV is updated at the next received character
(when RDRF = 1) after a write to the LPR regis-
ter
Notes:
- If no write to LPR is performed between the set-
ting of LDUM bit and the reception of the next
character, LDIV will be updated with the old value.
- After LDUM has been set, it is possible to reset
the LDUM bit by software. In this case, LDIV can
be modified by writing into LPR / LPFR registers.
Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.
These bits configure the LIN mode:
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR reg-
isters are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
– Management of LIN Headers.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
– LIN Parity Checking (in conjunction with the
PCE bit)
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only us-
able in LIN Slave mode. It enables the Header De-
tection Method. In addition if the RWU bit in the
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
7
0
LDUM
LINE
LSLV
LASE
LHDM
LHIE LHDF
LSF
LINE
LSLV
Meaning
0
x
LIN mode disabled
1
0
LIN Master Mode
1
LIN Slave Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72P361J4TA | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F321BAR7TARE | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64 |
| ST72P321B(AR6)TCXXXE | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| ST72F324BJ2TATRE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72F324BK4TCE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72361K6T6 | 制造商:STMicroelectronics 功能描述:ROMLESS MICRO WITH 2 UART - Bulk |
| ST72371 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
| ST72371N4B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
| ST72371N4B1/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|ST72 CPU|CMOS|SDIP|56PIN|PLASTIC |
| ST72371N4T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
發(fā)布緊急采購，3分鐘左右您將得到回復。