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參數(shù)資料
| 型號： | ST72361AR9TC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 39/224頁 |
| 文件大?。?/td> | 4821K |
| 代理商： | ST72361AR9TC |
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ST72361-Auto
133/224
LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1)This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: In SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
1: Receiver is enabled and begins searching for a
start bit
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 77).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 77).
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
1)
SBK1)
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
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