參數(shù)資料
型號(hào)： SST-MELODY-DAP
英文描述： SST-Melody&#174:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02)
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 585K
代理商： SST-MELODY-DAP
REV. 0
SST-Melody-DAP
–7–
Pin
No.
Mnemonic
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IRQE
+PF4
IRQL0
+PF5
GND
IRQL1
+PF6
IRQ2
+PF7
DT0
TFS0
RFS0
DR0
SCLK0
V
DDEXT
DT1
/
FO
TFS1/
IRQ1
RFS1/
IRQ0
DR1/FI
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
Pin
No.
Mnemonic
1
2
3
4
5
6
7
8
9
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
V
DDEXT
CLKOUT
GND
V
DDINT
WR
RD
BMS
DMS
PMS
IOMS
CMS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin
No.
Mnemonic
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/
IACK
V
DDINT
GND
D4/
IS
D5/IAL
D6/
IRD
D7/
IWR
D8
GND
V
DDEXT
D9
D10
D11
GND
D12
D13
D14
D15
Pin
No.
Mnemonic
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [MODE D]
PF2 [MODE C]
V
DDEXT
PWD
GND
PF1 [MODE B]
PF0 [MODE A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
The LQFP package pinout is shown in the Pin Function Descriptions. Pin names in bold text replace the plain text named functions
when Mode C = 1. A plus (+) sign separates two functions when either function can be active for either major I/O mode. Signals
enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
The multiplexed pins DT1/FO, TFS1/
IRQ1
, RFS1/
IRQ0
, and DR1/FI are mode selectable by setting Bit 10 (SPORT1 configure) of
the System Control register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt
and flag pins. This bit is set to 1 by default upon reset.
TIMING SPECIFICATIONS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, the user
cannot meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. There is no control over this. Timing circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell what the
processor will do in a given circumstance. Switching characteris-
tics may be used to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
MEMORY TIMING SPECIFICATIONS
Table I shows common memory device specifications and the
corresponding SST-Melody-DAP timing parameters, for your
convenience.
PIN FUNCTION DESCRIPTION
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