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參數(shù)資料
| 型號： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
–22–
SST-Melody-DAP
DMA
PROGRAM MEMORY
OVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000 –
0x3FFF
DMA
DATA MEMORY
OVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
0x0000 –
0x1FFF
IDMA AND SDMA HAVE SEPARATE DMA CONTROL REGISTERS.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IDMA OVERLAY
RESERVED SET TO 0
DM(0x3FE7)
IDDMOVLAY
IDPMOVLAY
SHORT READ ONLY
0 = ENABLE
1 = DISABLE
RESERVED SET TO 0
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IDMA CONTROL (U = UNDEFINED AT RESET)
DM(0x3FE70)
IDMAA ADDRESS
IDMAD DESTINATION MEMORY TYPE
0 = PM
1 = DM
RESERVED SET TO 0
RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
Figure 13. IDMA Control/OVLAY Registers
Figure 14. Direct Memory Access––PM and DM
Memory Maps
Bootstrap Loading (Booting)
The SST-Melody-DAP has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B, and C Configura-
tion bits.
When the MODE pins specify BDMA booting, the SST-Melody-
DAP initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register
is set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-chip
program memory to be loaded from byte memory. These 32 words
are used to set up the BDMA to load in the remaining program
code. The BCR bit is also set to 1, which causes program execu-
tion to be held off until all 32 words are loaded into on-chip
program memory. Execution then begins at Address 0.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host mode, the addresses
to boot memory must be constructed externally to the SST-
Melody-DAP. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
The SST-Melody-DAP can also boot programs through its
Internal DMA port. If Mode C = 1, Mode B = 0, and Mode
A = 1,
the
SST-Melody-DAP boots from the IDMA port. The
IDMA feature can
load as much on-chip memory as desired.
Program
execution is held off until on-chip program memory
location 0
is written to.
Bus Request and Bus Grant
The SST-Melody-DAP can relinquish control of the data and
address buses to an external device. When the external device
requires access to memory, it asserts the bus request (
BR
) signal.
If the SST-Melody-DAP is not performing an external memory
access, it responds to the active
BR
input in the following processor
cycle by:
Three-stating the data and address buses and the
PMS
,
DMS
,
BMS
,
CMS
,
IOMS
,
RD
, and
WR
output drivers,
Asserting the bus grant (
BG
) signal, and
Halting program execution.
If Go mode is enabled, the SST-Melody-DAP will not halt
program execution until it encounters an instruction that requires
an external memory access.
If the SST-Melody-DAP is performing an external memory
access when the external device asserts the
BR
signal, it will not
three-state the memory interfaces nor assert the
BG
signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
When the
BR
signal is released, the processor releases the
BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when
RESET
is active.
The BGH pin is asserted when the SST-Melody-DAP requires
the external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting the bus
request. Once the bus is released, the SST-Melody-DAP deasserts
BG and BGH and executes the external memory access.
Flag I/O Pins
The SST-Melody-DAP has eight general-purpose program-
mable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction: 1 = output and 0 = input. The PFDATA register
is used to read and write the values on the pins. Data being
read from a pin configured as an input is synchronized to the
SST-Melody-DAP’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, the SST-Melody-DAP
has five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2
are dedicated output flags. FI and FO are available as an alternate
configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
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