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參數(shù)資料
| 型號(hào)： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
SST-Melody-DAP
–21–
Table X. Data Formats
BTYPE
Internal Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally, the 14-
bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion of
the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it
can be used to check the status of the transfers. When it
reaches zero, the transfers have finished and a BDMA interrupt
is generated. The BMPAGE and BEAD registers must not be
accessed by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
The BDMA Overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. For SST-Melody-DAP, set to
zero BDMA Overlay bits in the BDMA Control register.
The BMWAIT field, which has four bits on SST-Melody-DAP,
allows selection up to 15 wait states for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA port provides an efficient means of communication
between a host system and the SST-Melody-DAP. The port is
used to access the on-chip program memory and data memory
of the DSP with only one DSP cycle per word overhead. The
IDMA port cannot, however, be used to write to the DSP’s
memory-mapped control registers. A typical IDMA transfer
process is described as follows:
1. Host starts IDMA transfer
2. Host checks
IACK
control line to see if the DSP is busy
3. Host uses
IS
and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of Bits 7:0 represent the IDMA overlay and bits 14:8
must
be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent
the starting address of internal memory to be accessed and
Bit 14 reflects PM or DM for access. For SST-Melody-DAP,
IDDMOVLAY and IDPMOVLAY bits in the IDMA Overlay
register should be set to zero.
4. Host uses
IS
and
IRD
(or
IWR
) to read (or write) DSP
internal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and databus and
supports 24-bit program memory. The IDMA port is completely
asynchronous and can be written while the SST-Melody-DAP is
operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (
IS
) latches
this value into the IDMAA register.
Once the address is stored, data can be read from or written to,
the SST-Melody-DAP’s on-chip memory. Asserting the select
line (
IS
) and the appropriate read or write line (
IRD
and
IWR
respectively) signals the SST-Melody-DAP that a particular
transaction is required. In either case, there is a one processor
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (
IS
) and address latch enable (IAL) directs
the SST-Melody-DAP to write the address onto the IAD0–14 bus
into the IDMA control register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown in Figure 13, is memory-
mapped at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host. For SST-Melody-
DAP, IDDMOVLAY and IDPMOVLAY bits in the IDMA
overlay register should be set to 0.
Refer to the following figures for more information on IDMA
and DMA memory maps.
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