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| 型號： | SST-MELODY-DAP |
| 英文描述： | SST-Melody®:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02) |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 585K |
| 代理商： | SST-MELODY-DAP |
REV. 0
SST-Melody-DAP
–19–
*
SEE TABLE VIII FOR DMOVLAY BITS
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
ACCESSIBLE WHEN
DMOVLAY = 1
ACCESSIBLE WHEN
DMOVLAY = 2
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
0x0000
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
DATA MEMORY
ADDR
EXTERNAL
MEMORY
0x0000–0x1FFF
0x0000–0x1FFF
*
0x0000–0x1FFF
*
Figure 8. Program Memory
Table VIII. DMOVLAY Bits
Program Memory
Program memory (Full Memory mode) is a 24-bit wide
space
for storing both instruction opcodes and data. The SST-Melody-
DAP has 16K words of program memory RAM on-chip, and
the capability of accessing up to two 8K external memory overlay
spaces using the external databus.
Program memory (Host mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
Host Mode due to a restricted databus that is 16 bits wide only.
Data Memory
Data memory (Full Memory mode) is a 16-bit wide space used
for the storage of data variables and for memory-mapped con-
trol registers. The SST-Melody-DAP has 16K words on
data memory RAM on-chip. Part of this space is used by
32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external databus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register and the Wait State mode bit.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WAIT STATE CONTROL
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 – N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 – 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0 3FFE)
Figure 9. Wait State Control Register
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
BMWAIT
DM(0 3FE6)
CMSSEL
0 = DISABLE
CMS
1 = ENABLE
CMS
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11–IOM, 10–BM, 9–DM, 8–PM)
Figure 10. Programmable Flag and Composite
Control Register
DMOVLAY
Memory
A13
A12:0
0
1
2
Internal
External Overlay 1
External Overlay 2
Not Applicable
0
1
Not Applicable
13 LSBs of Address between 0x2000 and 0x3FFF
13 LSBs of Address between 0x2000 and 0x3FFF
IACK
Configuration
Mode D = 0 and in Host Mode,
IACK
is an active, driven
signal and cannot be “Wire-Ored.”
Mode D = 1 and in Host Mode,
IACK
is an open drain and
requires an external pull-down, but multiple
IACK
pins can be
“Wire-Ored” together.
MEMORY ARCHITECTURE
The SST-Melody-DAP provides a variety of memory and pe-
ripheral
interface options. The key functional groups are
program
memory, data memory, byte memory, and I/O. Refer
to the following figures and tables for PM and DM memory
allocations in the SST-Melody-DAP.
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