參數(shù)資料
型號(hào)： SST-MELODY-DAP
英文描述： SST-Melody&#174:-DAP: Audio Processor Data Sheet (Rev. 0. 10/02)
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 585K
代理商： SST-MELODY-DAP
REV. 0
–12–
SST-Melody-DAP
Common-Mode Pins
Mnemonic
No. of Pins
I/O
Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
CLKIN, XTAL
CLKOUT
SPORT0
SPORT1
IRQ1
:
IRQ0
, FI, FO
PWD
PWDACK
FL0, FL1, FL2
V
DDINT
V
DDEXT
GND
V
DDINT
V
DDEXT
GND
EZ-Port
1
1
1
1
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
I/O
I/O
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Level-Sensitive Interrupt Requests
1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
1
Programmable I/O Pin
Mode Select Input—Checked Only During
RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During
RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During
RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During
RESET
Programmable I/O Pin During Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO
2
Power-Down Control Input
Power-Down Control Output
Output Flags
Internal V
DD
(2.5 V) Power (LQFP)
External V
DD
(2.5 V or 3.3 V) Power (LQFP)
Ground (LQFP)
Internal V
DD
(2.5 V) Power (Mini-BGA)
External V
DD
(2.5 V or 3.3 V) Power (Mini-BGA)
Ground (Mini-BGA)
For Emulation Use
1
1
1
1
1
1
1
2
1
5
5
1
1
3
2
4
10
4
7
20
9
I
O
O
I
I
I
I
I
I
I/O
NOTES
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices, or set as a programmable flag.
SPORT configuration determined by the DSP System Control Register. Software configurable.
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