參數(shù)資料
型號： SM3E-19.44M
廠商： Connor-Winfield
文件頁數(shù)： 34/36頁
文件大小： 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類型： 定時模塊，系統(tǒng)時鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 7 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Detailed Description continued
TheM/SOutputortheOutput1ofeachdevicemaybecross-connectedtotheotherdevice’sM/SRefinput.Thedeviceauto-
detectsthefrequencyontheM/SRefinput.MasterorslavestateofadeviceisdeterminedbytheM/Spin.Thus,master/slavestateis
alwaysmanuallycontrolledbytheapplication.Themastersynchronizestotheselectedinputreference,whiletheslavesynchronizes
totheM/SRefinput.(Notethat8kHzframephasealignmentismaintainedacrossamaster/slavepairofdevicesonlyifM/SOutputis
usedasthecrosscouplesignal.)
Theunitoperatinginslavemodelocksonandphase-alignstothecross-referenceclock(M/SOutputorOutput1)fromtheunit
inmastermode.Thephaseskewbetweentheinputcross-referenceandtheoutputclockfortheslaveunitistypicallylessthan±1ns
(under±3nsindynamicsituations,includingreferencejitterandwander).
PerfectphasealignmentofthetwoOutput1outputclockswouldrequirenodelayonthecross-referenceclockconnection.To
accommodatepathlengthdelays,theSM3Eprovidesaprogrammablephaseskewfeature.Theslave’sOutput1orM/SOutputmay
bephaseshifted-32nSto+31.75nSrelativetoM/SInputaccordingtothecontentsoftheMS_Phase_Offsetregistertocompensate
forthepathlengthoftheM/SOutputorOutput1toM/SInputconnection.Thisoffsetmaythereforebeprogrammedtoexactly
compensatefortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmayfurther
beadjustedtoaccommodateanyoutputclockdistributionpathdelaydifferences.Thus,master/slaveswitcheswiththeSM3devices
maybeaccomplishedwithnear-zerophasehits.
Thefirsttimeaunitbecomesaslave,suchasimmediatelyafterpower-up,itsoutputclockphasestartsoutarbitrary,andwill
quicklyphase-aligntothecross-referencefromthemasterunit.Thephaseskewwillbeeliminated(orconvergedtotheprogrammed
phaseoffset)stepbystep.Thewholepull-in-and-lockprocesswillcompleteinabout60seconds.Thereisnofrequencyslew
protectioninslavemode.Inslavemode,theunit’smissionistolocktoandfollowthemaster.
Onceapairofunitshasbeenoperatinginalignedmaster/slavemode,andamaster/slaveswitchoccurs,theunitthatbecomes
masterwillmaintainitsoutputclockphaseandfrequencywhileaphasebuild-out(tothecurrentoutputclockphase)isperformedon
itsselectedreferenceinput.Therefore,asmastermodeoperationcommences,therewillbenophaseorfrequencyhitsontheclock
output.
Likewise,theunitthatbecomestheslavewillmaintainitsoutputclockfrequencyandphasefor1msecbeforestartingtofollowthe
cross-reference,protectingthedownstreamclockusersduringtheswitch.Assumingthephaseoffsetisprogrammedfortheactual
propagationdelayofthiscross-referencepath,therewillagainbenophasehitsontheoutputclockoftheunitthathastransitioned
frommastertoslave.
Master / Slave Configuration
Figure 3
STC3500
SM3E
M/S_OUT / OUTPUT1 / BITS
M/S REF
REFS1-8
M/S REF
2
SM3E
1
Furthermore,underregisteraccesscontrol,abackupholdoverhistoryregisterisprovided.Itmaybeloadedfromtheactive
holdoverhistoryorrestoredtotheactiveholdoverhistory.Theactiveholdoverhistorymayalsobeflushed.
Holdovermodemaybeenteredatanytime.Ifthereisnoholdoverhistoryavailable,theprioroutputfrequencywillbemaintained.
Wheninholdover,theapplicationmayread(viaregisteraccess)thetimesinceholdoverwasenterred.
Master/Slave Operation
PairsofSM3Edevicesmaybeoperatedinamaster/slaveconfigurationforredundanttimingsourceapplications.Atypical
configurationisshownbelow.:
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