參數(shù)資料
型號(hào)： SM3E-19.44M
廠商： Connor-Winfield
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類型： 定時(shí)模塊，系統(tǒng)時(shí)鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 26 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Application Notes continued
Master/Slave Configuration–Apairofdevicesareinterconnectedbycross-couplingtheirrespectiveM/S Outputs or
Output1totheotherdevice’sM/S REFinput(SeeFigure8).Additionally,thereferenceinputsforeachdevicewouldtypicallybe
correspondinglythesame,sothatwhenaMaster/Slaveswitchoccurs,synchronizationwouldcontinuewiththesamereference.The
referencesmaybedrivenbythesamesignaldirectlyorviaseparatedrivers,astheredundancyofthatpartofthesystemrequires.
Distributionpathlengthsarenotcriticalhere,asaphasebuild-outwilloccurwhenadeviceswitchesfromslavetomaster.
ThepathlengthsofthetwoM/SOutputto
M/S REFsignalsisofinterest,however.Theyneednotbethesame.However,to
accommodatepathlengthdelays,theSM3Eprovidesaprogrammablephaseskewfeature,whichallowstheapplicationtooffsetthe
outputclockfromthecross-referencesignalby-32nsto+31.75ns.Thisoffsetmaythereforebeprogrammedtoexactlycompensate
fortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmaybefurtheradjusted
toaccommodateanyoutputclockdistributionpathdelaydifferences.PhaseoffsetisprogrammedbywritingtothePhase_Offset
register,andistypicallyaone-timedeviceinitializationfunction.(SeeregisterdescriptionandRegisterAccessControlsections).Thus,
master/slaveswitcheswiththeSM3Edevicesmaybeaccomplishedwithnear-zerophasehits.
ForapplicationsthatuseHardwareControlonly(i.e.phaseoffsetprogrammingisnotavailable),itisdesirabletokeepthecross
couplepathlengthsataminimumandrelativelyequalinlength,asthepathlengthwillappearasaphasehitintheslaveclockoutput
whenamaster/slaveswitchoccursinaHardwareControlconfiguration.
Master/Slave Operation and Control–TheMaster/Slavestateisalwaysmanuallycontrolledbytheapplication.Masterorslave
stateofadeviceisdeterminedbythe
MASTER SELECT pin.Choosingthemaster/slavestatesisafunctionoftheapplication,based
ontheconfigurationoftherestofthesystemandpotentialdetectedfaultconditions.
Master/slaveswitchesshouldbeperformedwithminimaldelaybetweenswitchingthestatesofeachofthetwodevices.Thiscan
beeasilyaccomplished,forexample,bycontrollingthemaster/slavestatewithasinglesignal,coupledtooneofthedevicesthrough
aninverter.WhileperformingMaster/Slaveswitches,onehastomakesurethatbothmodulesarenotinslavemode.Thiscreatesa
“TimingLoop”thatcancauseundesirableeffects.
InthecaseofRegisterAccessAutomaticControlmode,wherereferenceselectionisautomatic,itisnecessarytoreadthe
operationalmodeBITS3-0)fromthemaster’s
Op_Moderegisterandwriteittotheslave’sOp_Moderegister.Themaster’sreference
selectionwillthenbeusedbytheslavewhenitbecomesmaster.Inadditiontohavingthereferencespopulatedthesame,andinthe
sameorderforbothdevices,itisdesireabletowritethereferencefrequencyandpriorityregisters
Ref(1-8)_Frq_Priorityandthe
Ref_Maskregisterstothesamevaluesforbothdevicestoensureseamlessmaster/slaveswitches.
Reset–Deviceresetisaninitializationtimefunction,whichresetsinternallogicandregistervalues.Aresetisperformed
automaticallywhenthedeviceispoweredup.Registersreturntotheirdefaultvalues,asnotedintheregisterdescriptions.Device
modeandfunctionalityfollowingaresetaredeterminedbythestateofthevarioushardwarecontrolpins.
Holdover History Accumulation and Maintenance -- Holdoverhistoryaccumulationandmaintenancemaybecontrolledin
greaterdetailifregisterbusaccesstothedeviceisprovided.Holdoverhistoryaccumulationandcontrolencompassesthreedevice
internalregisters,threebusaccessregistersforcontrolandaccess,andtwostatusbitsintheDPLL_Statusregister.
Oncelockhasbeenachieved,holdoverhistoryiscompiledintheaccumulationregister.ItistransferredtotheActiveholdoverhistory
whenitisready(typicallyinabout15minutes).The“HoldoverAvailable”bitandoutputpinaresetto“1”.Fromthenon,theActive
holdoverhistoryiscontinuallyupdatedandkeptinsyncwiththeholdoverhistoryaccumulationregister.(SeeFigure11).
Hold Over History
Accumulation Register
Active
Hold Over History
Backup
Hold Over History
相關(guān)PDF資料
PDF描述
SM802104UMG TR IC SYNTHESIZER 2CH 24-QFN
SM802105UMG TR IC SYNTHESIZER 2CH 24-QFN
SM802108UMG IC SYNTEHSIZER 156.25MHZ 24QFN
SM802109UMG TR IC SYNTHESIZER QUAD 100MHZ 24QFN
SM840002KA TR IC CLK SYNTHESIZER LN 16-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SM3F-100TQ-ACTEL 功能描述:ADAPTER MODULE 100TQFP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 適配器 系列:* 標(biāo)準(zhǔn)包裝:96 系列:- 模塊/板類型:TQFP 插座模塊 適用于相關(guān)產(chǎn)品:-
SM3F-100VQ-ACT 制造商:Microsemi Corporation 功能描述:ACTEL VQ100 ADAPTER MODULES
SM3F-100VQ-ACTEL 功能描述:ADAPTER MODULE 100VQFP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 適配器 系列:* 標(biāo)準(zhǔn)包裝:96 系列:- 模塊/板類型:TQFP 插座模塊 適用于相關(guān)產(chǎn)品:-
SM3F-108QN-ACTEL 功能描述:ADAPTER MODULE 108QFN RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 適配器 系列:* 標(biāo)準(zhǔn)包裝:96 系列:- 模塊/板類型:TQFP 插座模塊 適用于相關(guān)產(chǎn)品:-
SM3F-121CS-ACTEL 功能描述:ADAPTER MODULE 121CSP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 適配器 系列:* 標(biāo)準(zhǔn)包裝:96 系列:- 模塊/板類型:TQFP 插座模塊 適用于相關(guān)產(chǎn)品:-
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*