參數(shù)資料
型號： SM3E-19.44M
廠商： Connor-Winfield
文件頁數(shù)： 17/36頁
文件大?。?/td> 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類型： 定時模塊，系統(tǒng)時鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 24 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
SM3E Initialization:
Power-up:
1.Ifpossible,alwaysstartupinmastermode.Afterthemoduleispoweredup,holdtheresetpinlowfor10ms.Wait1200ms
andreadthecontentsofregister0x33.Ifitreads1thenthemodulecameupproperly.Ifitreads0thenresetthemoduleandre-read
register0x33after1200ms.Thecontentsof0x33mustread1beforecontinuing.
2.Remaininthedefaultfree-runmodefor10secondsthenreadthevalueofbit1ofregister0x11orpin2,theLOLalarmoutput.
IftheLOLalarmisset,theresetpinmustbepulledlowasin1above.Inthefree-runmodetheLOLalarmshouldneverbeset.This
indicatesthemoduleisinaninvalidstate.IfthereisnoLOLalarminfree-runthemoduleisready.
Operation:
Onpoweruporafteraresetalltheregistersareloadedwiththeirdefaultvalues.Thedefaultvaluesofsomeimportantregisters
aregivenbelowassumingtheSM34moduleoperatesasaMaster
Address(Hex)
Register Name
Value(Binary MSB first)
Notes
0x03
Bandwidth_PBO
00000111
Bandwidth=0.098Hz
0x04
Ctl_Mode
0000r010
r-ReadOnly
0x05
Op_Mode
00010000
IndicatesFreerunmode
0x06
Max_Pullin_Range
01100100
0x0b
Ref_Mask
00000000
0x0d
Ref_Rev_Delay
00000101
0x0e
Phase_Offset
00000000
0x0f
Calibration
00000000
0x11
DPLL_Status
00000000
IndicatesNoActiveReference
0x13
Intr_Enable
00000000
IndicatesInterruptsaredisabled
0x1c-0x23
Ref(1-8)_Frq_Priority
xxxx0000
Frequenciesareautodetected
0x33
Chksum
xxxxxxx1
Bit0shouldbehightoindicatethat
datahasbeenloaded
correctlyfromtheEEPROM.
I.TheunitstartsupinFreeRunandoperatesinManualmode.Herearethestepsthatneedtobetakentolocktheunittoa
referenceinManualmode.
1.
Applysignaltothereferenceinputs.
2.
Settheappropriatepullinrangebywritingtoaddress0x06.
3.
Avalueof0001xxxx,dependingonwhich(Ref1-8)referencetolockto,shouldbewrittentoaddress0x05.
4.
EnableReferencemaskforappropriatereferencesbywritinga1tothereferencebitinaddress0x0b.
5.
EnableallInterruptsbywriting11111111toaddress0x13.
II.Tolocktheunittoareferenceinautonomous(automatic)modeafterpoweruporreset,thefollowingstepsshouldbetaken.
YoucanalsoswitchfromManualtoAutonomousmodedirectly.Whendoingso,pleaseensurethattheappropriatereferencesare
availablebycheckingREF_AVAILABLEregister(address:0x0c).
1.
Clearbit1ofCTL_MODEregister(address:0x04).Thisputsthemoduleinautonomousmode.
2.
Applysignaltothereferenceinputs
3.
Settheappropriatepullinrangebywritingtoaddress0x06
4.
Thedefaultbandwidthof0.098HzisappropriateforStratum3operation.
5.
EnableReferencemaskforappropriatereferencesbywritinga1tothereferencebitinaddress0x0b.
6.
SetpriorityandrevertivityfortheinputreferencesbywritingtotheappropriateRef_Frq_Priorityregisters(bits3-0).
7. EnableallInterruptsbywriting11111111toaddress0x13.
8. Settheunittooperateinautonomousmodebyclearingbit1ofaddress0x04
III.SlaveModeOperation:
1.
AsaSlave,themoduleoperatesinAutonomousmode.
2.
TheBandwidthisset,bydefault,to1.6Hz(Bandwidth_PBOregister(Address0x03):00001011).
3.
Notethatbit4oftheOP_MODEregister(Address0x05)iscleared.
4.
ThevaluesinBits3-0ofthisregisterhavenoeffectontheoperationoftheSlavemodule.
5.
FortheSlavemoduletotracktheMasteraccurately,anappropriatePhaseOffsetvalueshouldbewrittento
PHASE_OFFSETregister(Address0x0e),tocompensateforthepathdelay.
6.
ThemodulewilllocktotheCrossReferenceInput(XREF)fromthemaster.
IVRESETParameters:
1.
Theresetpinshouldbeheldlowforaminimumof10millisecondstoensureacompleteresetoccurs.
2. TheSPIinterfaceshouldnotbeaccessedforaminimumof1200msaftertheresetpinisde-asserted.
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