參數(shù)資料
型號： SM3E-19.44M
廠商： Connor-Winfield
文件頁數(shù)： 33/36頁
文件大小： 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準包裝： 1
系列： SM3
類型： 定時模塊，系統(tǒng)時鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 6 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
TheSM3Eutilizesupto8externalreferences,eachfrom8kHzto77.76MHz,maybeequippedandmonitoredforsignalpresence
andfrequencyoffset.Additionally,across-couple8kHzreferenceinputisprovidedformaster/slaveoperation.Referenceselection
maybemanualorautomatic,accordingtopre-programmedpriorities.Allreferenceswitchesareperformedinahitlessmanner,and
frequencyrampcontrolsensuresmoothoutputsignaltransitions.Whenreferencesareswitched,thedeviceprovidesacontrollable
phasebuild-outtominimizephasetransitionsintheoutputclocks.
Threeoutputsignalsareprovided,thefirstupto77.76MHz,thesecondfixedat8kHzforuseasaframesyncsignalaswellas
across-couplereferenceformaster/slaveoperation.Inslavemode,theoutputphasemaybeadjustedfrom-32to+31.75nSrelative
tothemaster,toaccommodatedownstreamsystemneeds,suchasdifferentclockdistributionpathlengths.ThethirdoutputisaBITS
clock,selectableaseither1.544MHzor2.048MHz.
DeviceoperationmaybeinFreeRun,locked,orHoldOvermodes.InFreeRun,theclockoutputsaresimplydeterminedbythe
FreeRunfrequencyandaccuracyofthecalibratedinternalclock.Inlockedmode,thechipphaselockstotheselectedinputreference.
Whilelocked,afrequencyhistoryisaccumulated.InHoldOvermode,thechipoutputsaregeneratedaccordingtothishistory.
TheDigitalPhaseLockedLoopprovidescriticalfilteringandfrequency/phasecontrolfunctionsthatmeetorexceedall
requirementsincriticaljitterandaccuracyperformanceparameters.Filterbandwidthmaybeconfiguredtosuitapplications
requirements.
ControlfunctionsareprovidedviastandardSPIbusregisterinterface.Registeraccessprovidesvisibilityintoavarietyofregistered
informationaswellasprovidingextensiveprogrammablecontrolcapability.
Operating Modes: The SM3E Operates in Either Free Run, Locked, or Hold Over Mode:
Free Run–InFreeRunmode,Output 1, M/S_Out, and BITS_Clk,theoutputclocks,aredetermineddirectlyfromandhavethe
accuracyofthecalibratedfreerunninginternalclock.Referenceinputscontinuetobemonitoredforsignalpresenceandfrequency
offset,butarenotusedtosynchronizetheoutputs.
Locked–TheOutput 1, M/S_Out, andBITS_Clk,outputsarephaselockedtoandtracktheselectedinputreference.Upon
enteringtheLockedmode,thedevicebeginsanacquisitionprocessthatincludesreferencequalificationandfrequencyslewrate
limiting,ifneeded.Oncesatisfactorylockisachieved,the“Locked”bitissetintheDPLL_Statusregister,andacompilationofthe
frequencyhistoryoftheselectedreferenceisstarted.WhenausableHoldOverhistoryhasbeenestablished,the
Hold_Goodpinis
set,andthe“HoldOverAvailable”bitissetinthe
DPLL_Statusregister.
PhasecomparisonandphaselockloopfilteringoperationsintheSM3Earecompletelydigital.Asaresult,deviceandloop
behaviorareentirelypredictable,repeatable,andextremelyaccurate.Carefullydesignedandprovenalgorithmsandtechniques
ensurecompletelyhitlessreferenceswitches,operationalmodechanges,andmaster/slaveswitches.
Basicloopbandwidthisprogrammablefrom0.84mHzto1.6Hertz,givingtheuserawiderangeofcontroloverthesystem
response.
Whenanewreferenceisacquired,maximumfrequencyslewlimitsensuresmoothfrequencychanges.Oncelockisachieved,
(<700secondsforStratum3E),the“Locked”bitisset.IftheSM3Eisunabletomaintainlock,LossofLock
(LOL)isasserted.All
transitionsbetweenlocked,HoldOverandFreeRunmodesareperformedwithminimalphaseeventsandsmoothfrequencyand
phasetransitions.
Referencephasehitsorphasedifferencesencounteredwhenswitchingreferences(orwhenenteringlockedmode)arenulled
outwithanautomaticphasebuild-outfunction.Phasebuild-outisperformedwitharesidualphaseerroroflessthan1nS,andcan
optionallybedisabledforhitsontheselectedreference,asrequiredforStratum3E.
Hold Over–UponenteringHoldOvermode,theOutput 1, M/S_Out, and BITS_Clk,outputsaredeterminedfromtheHoldOver
historyestablishedforthelastselectedreference.OutputfrequencyisdeterminedbyaweightedaverageoftheHoldOverhistory,and
accuracyisdeterminedbytheinternalclock.HoldOvermodemaybeenteredmanuallyorautomatically.AutomaticentryintoHold
Overmodeoccurswhenoperatingintheautomaticmode,thereferenceislost,andnoothervalidreferenceexists.Thetransferinto
andoutofHoldOvermodeisdesignedtobesmoothandfreeoftransients.Thefrequencyslewisalsolimitedtoamaximumof±2
ppm/sec.
Thehistoryaccumulationalgorithmusesafirstorderfrequencydifferencefilteringalgorithm.Typicalholdoveraccumulationtakes
about15minutes.Whenausableholdoverhistoryhasbeenestablished,the
Hold_Good pinisset,andthe“HoldoverAvailable”bitis
setinthe
DPLL_Status register.Theholdoverhistorycontinuestobeupdatedafter“HoldoverAvaialble”isdeclared.
ThealgorithmaccumulatestheholdoverhistoryonlywhenithaslockedoneitheranexternalreferenceinMasteroperationorthe
M/S Ref clockinSlaveoperation,starting15minutesafterpowerup.Trackingwillbesuspendedautomaticallywhenswitchingtoa
newreferenceandinFreeRunorHoldOvermode.Asetofregistersallowstheapplicationtocontrolaholdoverhistorymaintenance
policy,enablingeitherare-buildorcontinuanceofthehistorywhenareferenceswitchoccurs.
Detailed Description
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