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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 7/35頁 |
| 文件大小： | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MEMORY AND PARALLEL I/O INTERFACE READ
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
MIN
MAX
UNIT
tsu(AV-RDL)
Setup time, address valid before RD low
H–10
ns
th(RDH-AV)
Hold time, address valid after RD high
0
ns
tw(RDL)
Pulse duration, RD low§
H–2
ns
tw(RDH)
Pulse duration, RD high§
H–2
ns
td(RDH-WEL)
Delay time, RD high to WE low
2H – 5
ns
A15 – A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 8 for address-bus timing variation with load capacitance.
§ STRB and RD timing is – 3/+5 ns from CLKOUT1 timing on read cycles, following the first cycle after reset, which is always a seven wait-state cycle.
Values are derived from characterization data and are not tested.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)]
MIN
MAX
UNIT
ta(RDAV)
Access time, read data valid from address valid
2H – 15
ns
ta(RDL-RD)
Access time, read data valid after RD low
H–10
ns
tsu(RD-RDH)
Setup time, read data valid before RD high
10
ns
th(RDH-RD)
Hold time, read data valid after RD high
0
ns
See Figure 8 for address-bus timing variation with load capacitance.
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