參數(shù)資料
型號(hào)： SM320C50HFGM66
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 66 MHz, OTHER DSP, CQFP132
封裝： TIE BAR, CERAMIC, QFP-132
文件頁(yè)數(shù)： 14/35頁(yè)
文件大?。?/td> 536K
代理商： SM320C50HFGM66
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
EXTERNAL DMA TIMING
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 2)
PARAMETER
MIN
MAX
UNIT
td(HOL-HAL)
Delay time, HOLD low to HOLDA low
4H
ns
td(HOH-HAH)
Delay time, HOLD high before HOLDA high
2H
ns
tdis(AZ-HAL)
Disable time, address in the high-impedance state before HOLDA low§
H–15
ns
ten(HAH-Ad)
Enable time, HOLDA high to address driven
H–5
ns
td(XBL-IQL)
Delay time, XBR low to IAQ low
4H
6H
ns
td(XBH-IQH)
Delay time, XBR high to IAQ high
2H
4H
ns
td(XSL-RDV)
Delay time, read data valid after XSTRB low
40
ns
th(XSH-RD)
Hold time, read data after XSTRB high
0
ns
ten(IQL-RDd)
Enable time, IAQ low to read data driven
0
2H
ns
tdis(W)
Disable time, XR/W low to data in the high-impedance state
0
15
ns
tdis(I-D)
Disable time, IAQ high to data in the high-impedance state
H
ns
ten(D-XRH)
Enable time, data from XR/W going high
4
ns
Values derived from characterization data and are not tested.
HOLD is not acknowledged until current external access request is complete.
§ This parameter includes all memory control lines.
This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the SMJ320C50x data
lines become valid.
NOTE 2: X preceding a name refers to the external drive of the signal.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
td(HAL-XBL)
Delay time, HOLDA low to XBR low#
0#
ns
td(IQL-XSL)
Delay time, IAQ low to XSTRB low#
0#
ns
tsu(AV-XSL)
Setup time, Xaddress valid before XSTRB low
15
ns
tsu(DV-XSL)
Setup time, Xdata valid before XSTRB low
15
ns
th(XSL-D)
Hold time, Xdata hold after XSTRB low
15
ns
th(XSL-WA)
Hold time, write Xaddress hold after XSTRB low
15
ns
tw(XSL)
Pulse duration, XSTRB low
45
ns
tw(XSH)
Pulse duration, XSTRB high
45
ns
tsu(RW-XSL)
Setup time, R/W valid before XSTRB low
20
ns
th(XSH-RA)
Hold time, read Xaddress after XSTRB high
0
ns
# XBR, XR/W, and XSTRB lines should be pulled up with a 10-k
resistor to assure that they are in an inactive (high) state during the transition
period between the SMJ320C50x driving them and the external circuit driving them.
NOTE 2. X preceding a name refers to the external drive of the signal.
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