參數(shù)資料
型號(hào)： SM320C50HFGM66
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 66 MHz, OTHER DSP, CQFP132
封裝： TIE BAR, CERAMIC, QFP-132
文件頁數(shù)： 11/35頁
文件大?。?/td> 536K
代理商： SM320C50HFGM66
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RESET, INTERRUPT, AND BIO
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)]
PARAMETER
MIN
MAX
UNIT
tsu(IN-COL)
Setup time, INT1 – INT4, NMI, before CLKOUT1 low
15
ns
th(COL-IN)
Hold time, INT1 – INT4, NMI, after CLKOUT1 low
0
ns
tw(INL)SYN
Pulse duration, INT1 – INT4, NMI low, synchronous
4H+15
ns
tw(INH)SYN
Pulse duration, INT1 – INT4, NMI high, synchronous
2H+15§
ns
tw(INL)ASY
Pulse duration, INT1 – INT4, NMI low, asynchronous
6H+15
ns
tw(INH)ASY
Pulse duration, INT1 – INT4, NMI high, asynchronous
4H+15
ns
tsu(RS-X2L)
Setup time, RS before X2/CLKIN low
10
ns
tw(RSL)
Pulse duration, RS low
12H
ns
td(RSH)
Delay time, RS high to reset vector fetch
34H
ns
tw(BIL)SYN
Pulse duration, BIO low, synchronous
15
ns
tw(BIL)ASY
Pulse duration, BIO low, asynchronous
H+15
ns
tsu(BI-COL)
Setup time, BIO before CLKOUT1 low
15
ns
th(COL-BI)
Hold time, BIO after CLKOUT1 low
0
ns
These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to assure internal synchronization.
If in IDLE2, add 4H to these timings.
§ Values are specified by design and not tested.
Values derived from characterization data and are not tested.
tsu(IN-COL)
BIO
RS
X2/CLKIN
tsu(RS-X2L)
tsu(BI-COL)
tsu(IN-COL)
th(COL-BI)
tw(INH)SYN
A15 – A0
tw(INL)SYN
tsu(IN-COL)
th(COL-IN)
tw(BIL)SYN
td(RSH)
CLKOUT1
tw(RSL)
INT4 –
INT1
Figure 11. Reset, Interrupt, and BIO Timings
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