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參數(shù)資料
| 型號： | SM320C50HFGM66 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 66 MHz, OTHER DSP, CQFP132 |
| 封裝： | TIE BAR, CERAMIC, QFP-132 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大小： | 536K |
| 代理商： | SM320C50HFGM66 |
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
MIN
MAX
UNIT
tsu(AV-IQL)
Setup time, address valid before IAQ low
H–12
ns
th(IQL-AV)
Hold time, address valid after IAQ low
H–10
ns
tw(IQL)
Pulse duration, IAQ low
H–10
ns
td(CO-TU)
Delay time, CLKOUT1 falling to TOUT
–6
6
ns
tsu(AV-IKL)
Setup time, address valid before IACK low§
H–12
ns
th(IKH-AV)
Hold time, address valid after IACK high §
H–10
ns
tw(IKL)
Pulse duration, IACK low
H–10
ns
tw(TUH)
Pulse duration, TOUT high
2H – 12
ns
td(CO-XFV)
Delay time, XF valid after CLKOUT1
0
12
ns
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on, or code is executing off-chip).
§ IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 – A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
CLKOUT1
STRB
IACK
IAQ
ADDRESS
td(CO-TU)
tw(IKL)
tsu(AV-IKL)
tsu(AV-IQL)
tw(IQL)
th(IKH-AV)
th(IQL-AV)
XF
TOUT
td(CO-XFV)
tw(TUH)
td(CO-TU)
NOTE: IAQ and IACK are not affected by wait states.
Figure 12. IAQ, IACK, and XF Timings Example With Two External Wait States
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