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參數(shù)資料
| 型號： | SI5315A-C-GMR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 40/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULT 8KHZ-644.53MHZ 36QFN |
| 應(yīng)用說明： | SI5315/17 Crystal Selection AppNote |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘/頻率倍增器，抖動(dòng)衰減器，多路復(fù)用器 |
| PLL： | 無 |
| 主要目的： | 以太網(wǎng)，SONET/SDH/PDH，電信 |
| 輸入： | CML，CMOS，LVDS，LVPECL |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 644.53MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
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Si5315
Rev. 1.0
45
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled. Bypass mode is
not supported with CMOS clock outputs (SFOUT = LH).
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input:
If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the holdover state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
23
22
BWSEL1
BWSEL0
I3-Level
Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 20 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2NT-MY-S | CONVERTER MOD DC/DC 6.5V 50W |
| VE-B3W-IU | CONVERTER MOD DC/DC 5.5V 200W |
| VE-B3T-IU | CONVERTER MOD DC/DC 6.5V 200W |
| VE-2NR-MY-S | CONVERTER MOD DC/DC 7.5V 50W |
| VE-B3P-IU | CONVERTER MOD DC/DC 13.8V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5315B-C-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Prgrmmbl SyncE Clck Mlt/Jttr Attntr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5315B-C-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5315-C | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5315-C(B) | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5315-C_1 | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
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