參數(shù)資料
型號(hào): SI5315A-C-GMR
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 30/54頁(yè)
文件大?。?/td> 0K
描述: IC CLK MULT 8KHZ-644.53MHZ 36QFN
應(yīng)用說(shuō)明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL: 無(wú)
主要目的: 以太網(wǎng),SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 644.53MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5315
36
Rev. 1.0
6.2. Output Clock Drivers
The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0]
pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for
output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L
(ground), M (VDD/2), and H (VDD). Table 17 shows the signal formats based on the supply voltage and the type of
load being driven.
Figure 15. Typical Differential Output Circuit
Figure 16. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals. The CKOUT+/- can be
externally shorted together for greater drive strength specified in Table 2, “DC Characteristics”.
Table 17. Output Signal Format Selection (SFOUT)
SFOUT[1:0]
Signal Format
HL
CML
HM
LVDS
LH
CMOS
LM
Disabled
MH
LVPECL
ML
Low-swing LVDS
All Others
Reserved
Si5315
Rcvr
100
Z0 = 50
CKOUTn
CMOS
Logic
CKOUTn
Optionally Tie CKOUTn
Outputs Together for Greater Strength
Si5315
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