參數(shù)資料
型號： SI5315A-C-GMR
廠商： Silicon Laboratories Inc
文件頁數(shù)： 10/54頁
文件大?。?/td> 0K
描述： IC CLK MULT 8KHZ-644.53MHZ 36QFN
應(yīng)用說明： SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝： 250
系列： DSPLL®
類型： 時鐘/頻率倍增器，抖動衰減器，多路復(fù)用器
PLL： 無
主要目的： 以太網(wǎng)，SONET/SDH/PDH，電信
輸入： CML，CMOS，LVDS，LVPECL
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 644.53MHz
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 帶卷 (TR)
Si5315
18
Rev. 1.0
4.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 9 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value Aj0. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
lower input jitter frequencies.
Figure 9. Jitter Tolerance Mask/Template
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth
(i.e., BW):
For example, the jitter tolerance when fin = 19.44 MHz, fout = 161.13 MHz and the loop bandwidth (BW) is 113 Hz:
4.2.4. Jitter Attenuation Performance
The Internal VCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the reference input. (See 5.5. "Holdover Mode" on page 32.) In holdover, the Si5315's output clock stability
matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based
on the stability requirements of the application if holdover is a key requirement.
However, care must be exercised in certain areas for optimum performance. For examples of connections to the
Input
Jitter
Amplitude
Aj0
–20 dB/dec.
fJitter In
Excessive Input Jitter Range
BW/100 BW/10
BW
A
j0
5000
BW
------------- ns pk-pk
=
A
j0
5000
113
-------------
44.24 ns pk-pk
==
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參數(shù)描述
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SI5315-C 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED
SI5315-C(B) 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED
SI5315-C_1 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED
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