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參數資料
| 型號： | SI5315A-C-GMR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 25/54頁 |
| 文件大小： | 0K |
| 描述： | IC CLK MULT 8KHZ-644.53MHZ 36QFN |
| 應用說明： | SI5315/17 Crystal Selection AppNote |
| 標準包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時鐘/頻率倍增器，抖動衰減器，多路復用器 |
| PLL： | 無 |
| 主要目的： | 以太網，SONET/SDH/PDH，電信 |
| 輸入： | CML，CMOS，LVDS，LVPECL |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 644.53MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
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Si5315
Rev. 1.0
31
The prioritization of clock inputs for automatic switching is shown in Table 14. This priority is hardwired in the
devices.
At power-on or reset, the valid CKINn with the highest priority (1 being the highest priority) is automatically
selected. If no valid CKINn is available, the device suppresses the output clocks and waits for a valid CKINn signal.
If the currently selected CKINn goes into an alarm state, the next valid CKINn in priority order is selected. If no valid
CKINn is available, the device enters holdover.
Operation in revertive and non- revertive is different when a signal becomes valid:
Revertive (AUTOSEL = H):
The device constantly monitors all CKINn. If a CKINn with a higher priority than
the current active CKINn becomes valid, the active CKINn is changed to the
CKINn with the highest priority.
Non-revertive (AUTOSEL = M): The active clock does not change until there is an alarm on the active clock. The
device will then select the highest priority CKINn that is valid. Once in holdover,
the device will switch to the first CKINn that becomes valid.
5.4. Alarms
Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the
alarm conditions for that alarm output are cleared.
5.4.1. Loss-of-Signal
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT output signal that is processed with other alarms to generate LOS1 and LOS2.
An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active. Similarly, an LOS condition on
CKINn causes the LOSn_INT alarm to become active. Once a LOSn_INT alarm is asserted on one of the input
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT after a valid input clock appears is listed in Table 3, “AC Characteristics”. If another error condition on
the same input clock is detected during the validation time then the alarm remains asserted and the validation time
starts over.
5.4.1.1. LOS Algorithm
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry over
samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input
clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a
LOSn_INT alarm is declared. Table 3, “AC Characteristics” gives the minimum and maximum amount of time for
the LOS monitor to trigger.
5.4.1.2. Lock Detect
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in (Table 3, “AC Characteristics”). The LOL pin is also held in the
active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop
bandwidth (See Table 15).
Table 14. Input Clock Priority for Auto Switching
Priority
Input Clocks
1CKIN1
2CKIN2
3
Holdover
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相關代理商/技術參數 |
參數描述 |
|---|---|
| Si5315B-C-GM | 功能描述:時鐘發(fā)生器及支持產品 Pin-Prgrmmbl SyncE Clck Mlt/Jttr Attntr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5315B-C-GMR | 功能描述:時鐘發(fā)生器及支持產品 Pin-Ctrl SyncE Clk Xplier/Jitt Attn 2/2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5315-C | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5315-C(B) | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
| SI5315-C_1 | 制造商:AUK 制造商全稱:AUK corp 功能描述:IRED |
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