參數(shù)資料
型號(hào): SI5315A-C-GMR
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 1/54頁(yè)
文件大小: 0K
描述: IC CLK MULT 8KHZ-644.53MHZ 36QFN
應(yīng)用說(shuō)明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL: 無(wú)
主要目的: 以太網(wǎng),SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 644.53MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Rev. 1.0 4/12
Copyright 2012 by Silicon Laboratories
Si5315
S YNCHRONOUS E THE RNET /TELECOM J ITTER A TTENUATI N G
C LOCK M ULTIPLIER
Features
Applications
Description
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous
Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE
EEC options 1 and 2 when paired with a timing card that implements the required
wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
644.53 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon
Laboratories' third-generation DSPLL technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is
user programmable, providing jitter performance optimization at the application level.
Functional Block Diagram
Provides jitter attenuation and frequency
translation between SONET/PDH and
Ethernet
Supports ITU-T G.8262 Synchronous
Ethernet equipment slave clock (EEC
option 1 and 2) requirements with
optional Stratum 3 compliant timing card
clock source
Two clock inputs/two clock outputs
Input frequency range: 8 kHz–644 MHz
Output frequency range: 8 kHz–644 MHz
Ultra low jitter:
0.23 ps RMS (1.875–20 MHz)
0.47 ps RMS (12 kHz–20 MHz)
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 to 8.4 kHz
Automatic/Manual hitless switching
and holdover during loss of inputs
clock
Programmable output clock signal
format: LVPECL, LVDS, CML or
CMOS
40 MHz crystal or XO reference
Single supply: 1.8, 2.5, or 3.3 V
On-chip voltage regulator with high
PSRR
Loss of lock and loss of signal alarms
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 C
Synchronous Ethernet line cards
SONET OC-3/12/48 line cards
PON OLT/ONU
Carrier Ethernet switches routers
MSAN / DSLAM
T1/E1/DS3/E3 line cards
DSPLL
Clock In 1
Clock In 2
Clock Out 1
Clock Out 2
Clock 2 Disable/PLL Bypass
Output Signal Format[1:0]
XTAL/Clock
VDD (1.8, 2.5, or 3.3 V)
GND
Status/Control
Loss of Lock
Loss of Signal 2
Frequency Select[3:0]
Frequency Table Select
Manual/Auto Clock Selection
Clock Switch/Clock Active Indicator
Loss of Signal 1
Loop Bandwidth Select[1:0]
XTAL/Clock
Si5315
Ordering Information:
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
AUTOSEL
RST
LOS2
LOS1
GND
VDD
XA
VDD
XT
A
L
/CL
O
CK
IN
2+
CKI
N
2–
D
B
L2_BY
GN
D
CKI
N
1+
CKI
N
1–
CS_CA
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CKO
U
T1
SFO
U
T1
GN
D
VD
D
SF
OUT0
CKOU
T2
CKOU
T2
+
NC
GND
Pad
FRQSEL0
GND
9
18
19
28
XB
LO
L
GND
CKO
UT1+
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