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參數(shù)資料
| 型號(hào)： | SI4711-B30-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 380K |
| 描述： | IC TX FM RADIO 76-108MHZ 20UQFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 頻率： | 76MHz ~ 108MHz |
| 應(yīng)用： | 通用 |
| 調(diào)制或協(xié)議： | FM |
| 電流 - 傳輸： | 18.8mA |
| 數(shù)據(jù)接口： | PCB，表面貼裝 |
| 天線連接器： | PCB，表面貼裝 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 20-UFQFN 裸露焊盤 |
| 包裝： | 托盤 |
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Si4710/11-B30
Rev. 1.1
21
5.3. Digital Audio Interface
The digital audio interface operates in slave mode and
supports 3 different audio data formats:
1. I
2
S
2. Left-Justified
3. DSP Mode
5.3.1. Audio Data Formats
In I
2
S mode, the MSB is captured on the second rising
edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is low, and the Right Channel is transferred when the
DFS is high.
In Left-Justified mode, the MSB is captured on the first
rising edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is high, and the Right Channel is transferred when the
DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1 DCLK period. The Left Channel is transferred first,
followed right away by the Right Channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
5.3.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
the audio baseband processor. The sampling rate is
selected using the DIGITAL_INPUT_SAMPLE_RATE
property.
The device supports DCLK frequencies above 1 MHz.
After powerup the DIGITAL_INPUT_SAMPLE_RATE
property defaults to 0 (disabled). After DCLK is
supplied, the DIGITAL_INPUT_SAMPLE_RATE
property should be set to the desired audio sample rate
such as 32, 40, 44.1, or 48 kHz. The
DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.
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