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參數(shù)資料
| 型號(hào)： | SI3220PPTX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 72/112頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3220 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
62
Rev. 1.3
Not
Recommended
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3.18. Two-Wire Impedance Synthesis
Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop thus
minimizing the receive path signal reflected back onto
the transmit path. The Dual ProSLIC chipset provides
on-chip, digitally-programmable, two-wire impedance
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two-wire impedances are realized by
a programmable digital filter block. (See ZA and ZD
blocks in Figure 11 on page 25.)
Figure 33. Two-Wire Impedance Synthesis
Configuration
The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
Si322X coefficient generator software in the format RS +
the appropriate hex coefficients and loads them into the
appropriate control registers (registers 33–52). The two-
wire impedance can be set to any real or complex value
within the boundaries set in Table 34. The actual
impedance presented to the subscriber loop varies with
series impedance from protection devices placed
between the Dual ProSLIC chipset outputs and the TIP/
RING pair according to the following equation:
Where:
ZT is the termination impedance presented to the
TIP/RING pair
RPROT is the series resistance caused by protection
devices
RS is the series portion of the synthesized
impedance
RP||CP is the parallel portion of the synthesized
impedance
The user must enter the value of RPROT into the
software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
illustrates
the
simplified
two-wire
impedance
circuit
including
external
protection
resistors, where ZL is the actual line impedance for the
specific geographical region. The Dual ProSLIC devices
can accomodate up to 50
of series protection
impedance per leg.
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.
Figure 34. Two-Wire Impedance Simplified
Circuit
3.18.1. Impedance Synthesis Initialization
and Control
The Si322x utilizes a digital IIR filter to implement SLIC
impedance synthesis. Under normal operation, the
Si322x state machine controls the clocks to this filter
automatically such that the filter clocks are turned OFF
during those times when the filter is not required. During
pulse dialing, for example, the clocks are shut OFF
during the break period and turned back ON during the
make period.
When the clocks are shut OFF, the IIR filter holds the
last sample values in its storage elements. When the
Table 34. Two-Wire Impedance
Synthesis Limitations
Desired
Configuration
Programmable Limits
RS only
100–1000
RS + CP
RS x CP > 0.5 ms
RS + RP||CP
RS/(RS + RP) > 0.1
R
P
C
P
R
S
Z
T
2R
PROT
R
S
R
P
C
P
+
+
=
Dual
ProSLIC
Z
T
Z
L
R
PROT
R
PROT
S
i32
00
/2
TIP
RING
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