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| 型號： | SI3220PPTX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 58/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3220 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
Rev. 1.3
5
Not
Recommended
fo
r N
ew
D
esi
gn
s
High Battery Supply Voltage
VBATH
Continuous
–130
0.4
V
10 ms
–135
0.4
V
Low Battery Supply Voltage
VBAT,
VBATL
Continuous
VBATH
0.4
V
TIP or RING Voltage
VTIP,
VRING
Continuous
–130
0.4
V
Pulse < 10 us
VBATH–15
0.4
V
Pulse < 4 us
VBATH–35
0.4
V
TIP or RING Current
ITIP, IRING
–100
+100
mA
Thermal Information
Operating temperature (All devices)4
–40
+100
C
Storage temperature (All devices)
–40
+150
C
Thermal Resistance (Si3220/Si3225)5
JA
TQFP-64 ePad
25 (typical)
C/W
Thermal Resistance (Si3200/Si3202)5
JA
SOIC-16 ePad
55 (typical)
C/W
Table 1. Absolute Maximum Ratings and Thermal Information1 (Continued)
Parameter
Symbol
Test Condition
Min
Max
Unit
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded, and exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet.
2. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to
the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are
not exceeded under any operating condition in addition to providing thermal dissipation.
3. On Si3200 revision E, the dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/s.
4. Operation of the Si3220/Si3225 above 125
C junction temperature may degrade device reliability. The Si3200/Si3202
should be operated at a junction temperature below 140
C for optimal reliability.
5. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
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