參數(shù)資料
型號(hào)： SI3056SSI-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 83/94頁
文件大?。?/td> 0K
描述： BOARD EVAL SI3056/SI3018 SSI
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，數(shù)據(jù)采集裝置（DAA）
已用 IC / 零件： Si3056
已供物品： 板，CD
Si3056
Si3018/19/10
84
Rev. 1.05
7. Pin Descriptions: Si3056
Table 24. Si3056 Pin Descriptions
Pin #
Pin Name
Description
1MCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal clock or
modem/DSP.
2FSYNC
Frame Sync Output.
Data framing signal that indicates the start and stop of a communication/data frame.
3SCLK
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
4VD
Digital Supply Voltage.
Provides the 3.3 V digital supply voltage to the Si3056.
5SDO
Serial Port Data Out.
Serial communication data that is provided by the Si3056 to the modem/DSP.
6SDI
Serial Port Data In.
Serial communication and control data that is generated by the modem/DSP and pre-
sented as an input to the Si3056.
7
FC/RGDT
Secondary Transfer Request Input/Ring Detect.
An optional signal to instruct the Si3056 that control data is being requested in a sec-
ondary frame. When daisy chain is enabled, this pin becomes the ring detect output.
Produces an active low rectified version of the ring signal.
8
RESET
Reset Input.
An active low input that resets all control registers to a defined, initialized state. Also
used to bring the Si3056 out of sleep mode.
9C2A
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor C2. Used to communicate with the line-
side device.
10
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicate with the line-
side device.
FC/RGDT
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
MCLK
FSYNC
SCLK
V
D
SDO
SDI
RESET
OFHK
RGDT/FSD/M1
M0
V
A
GND
AOUT/INT
C1A
C2A
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