參數(shù)資料
型號(hào): SI3056SSI-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 63/94頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL SI3056/SI3018 SSI
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,數(shù)據(jù)采集裝置(DAA)
已用 IC / 零件: Si3056
已供物品: 板,CD
Si3056
Si3018/19/10
66
Rev. 1.05
Reset settings = 0010_1101
Register 23. Ring Validation Control 2
Bit
D7
D6D5D4
D3
D2D1D0
Name
RDLY[2]
RTO[3:0]
RCC[2:0]
Type
R/W
Bit
Name
Function
7
RDLY[2]
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
000
0 ms
001
256 ms
010
512 ms
.
1
11
1792 ms
6:3
RTO[3:0]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring thresh-
old crossing.
RTO[3:0]
Ring Timeout
0000
80 ms
0001
128 ms
0010
256 ms
.
1111
1920 ms
2:0
RCC[2:0]
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
Ring Confirmation Count Time
000
100 ms
001
150 ms
010
200 ms
011
256 ms
100
384 ms
101
512 ms
110
640 ms
111
1024 ms
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