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參數(shù)資料
| 型號： | SI3012 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| 中文描述： | 3.3伏催化裂化/ JATE直接訪問安排 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | SI3012 |
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Si3038
32
Rev. 2.01
Figure 29. AC-Link Audio Output Frame
The AC-link protocol provides for a special 16-bit time
slot (Slot 0) wherein each bit conveys a valid tag for its
corresponding time slot within the current audio frame.
A 1 in a given bit position of slot 0 indicates that the
corresponding time slot within the current audio frame
has been assigned to a data stream and contains valid
data. If a slot is tagged invalid, it is the responsibility of
the data source (the Si3024 for the input stream, the
AC’97 controller for the output stream) to populate all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs
at the beginning of each audio frame. The portion of the
audio frame where SYNC is high is called the Tag
Phase. The remainder of the audio frame where SYNC
is low is called the data phase. See Figure 28.
Additionally, for power savings, all clock, sync, and data
signals can be halted. The Si3038 chipset maintains its
register contents intact when entering a power-savings
mode.
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the
multiplexed bundles of all digital output data targeting
the Si3038’s DAC inputs and control registers. Each
audio output frame supports up to 12 20-bit outgoing
data time slots. Slot 0 is a special reserved time slot
containing
16
bits
used
infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT
slot 0, bit 15) which flags the validity for the entire audio
frame. If the Valid Frame bit is a 1, the current audio
frame contains at least one slot time of valid data. The
next 12 bit positions sampled by the Si3024 indicate
which of the corresponding 12 time slots contain valid
data. In this way, data streams of differing sample rates
can be transmitted across AC-link at its fixed 48-kHz
audio frame rate. Figure 29 illustrates the time slot-
based AC-link protocol.
A new audio output frame begins with a low to high
transition of SYNC. SYNC is synchronous to the rising
for
AC-link
protocol
edge of BIT_CLK. On the immediately following falling
edge of BIT_CLK, the Si3024 samples the assertion of
SYNC. This falling edge marks the time when both
sides of AC-link are aware of the start of a new audio
frame. On the next rising of BIT_CLK, the AC’97
controller transitions SDATA_OUT into the first bit
position of slot 0 (Valid Frame bit). Each new bit position
is presented to AC-link on a rising edge of BIT_CLK,
and subsequently sampled by the Si3024 on the
following falling edge of BIT_CLK. This sequence
ensures that data transitions and subsequent sample
points for both incoming and outgoing data streams are
time aligned. See Figure 30.
Figure 30. Start of an Audio Output Frame
SDATA_OUT’s composite stream is MSB justified (MSB
first) with all non-valid slots’ bit positions padded with 0s
by the AC’97 controller.
In the event that there are less than 20 valid bits within
an assigned and valid time slot, the AC’97 controller
always pads all trailing non-valid bit positions of the 20-
bit slot with 0s.
Variable Sample Rate Signaling Protocol
For variable sample rate output, the codec examines its
sample rate control registers, the state of its FIFOs, and
Tag Phase
Data Phase
20.8
μ
S
(48 KHz)
SYNC
SDATA_OUT
BIT_CLK
Valid
Frame
slot(1)
slot(2)
"0"
"0"
"0"
19
0
19
0
19
0
19
0
slot(12)
End of previous
Audio Frame
Time Slot "Valid"
Bits
("1" = Time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
12.228 MHz
81.4 nS
SYNC
SDATA_OUT
BIT_CLK
Valid
Frame
slot (1) slot (2)
AC '97 samples SNYC assertion here
AC '97 samples SDATA_OUT bit of frame here
End of previous
Audio Frame
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI3012-KT | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3035 | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| SI3034 | DESICCANT CLAY, 30G, PK400; RoHS Compliant: NA |
| SI3036 | Masking Tape; Tape Backing Material:Crepe Paper; Width:24mm; Roll Length:55m; Adhesive Material:Rubber; Color:Natural; Leaded Process Compatible:No; Pack Quantity:1 RoHS Compliant: Yes |
| SI3038 | Duct Tape; Tape Backing Material:PVC; Width:2"; Roll Length:50yard; Color:Gray; Features:Temperature-stable adhesive, Tears easily and evently by hand, leaves no stciky residue when removed RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI-3012KD | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Surface-Mount, Low Current Consumption, Low Dropout Voltage Linear Regulator ICs |
| SI-3012KD-TL | 制造商:Sanken Electric Co Ltd 功能描述:IC REG LDO ADJ 1A TO-263-5 |
| SI-3012KM | 制造商:SANKEN 制造商全稱:Sanken electric 功能描述:Surface Mount Low Current Consumption Low Dropout Voltage Linear Regulator ICs |
| SI-3012KS | 制造商:SANKEN 制造商全稱:Sanken electric 功能描述:Surface-Mount, Low Current Consumption, Low Dropout Voltage |
| Si3012-KS | 功能描述:射頻無線雜項 Si3035 FCC/JATE DAA SSI interface RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
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